LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 100

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.6
7.7
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
EPP 1.9 Write
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address
cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write
cycle can complete. The write cycle can complete under the following circumstances:
1.
2.
Write Sequence of operation
1.
2.
3.
4.
5.
6.
7.
8.
EPP 1.9 Read
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts
wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The
read cycle can complete under the following circumstances:
1.
2.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7. a)
8.
9.
b)
If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then
the write can complete when nWAIT goes inactive high.
If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before
changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is
determined inactive.
The host initiates an I/O write cycle to the selected EPP register.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the
WRITE signal is valid.
Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip
may begin the termination phase of the cycle.
a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase.
If it has not already done so, the peripheral should latch the information byte now.
b) The chip latches the data from the internal data bus for the PData bus and drives the sync that
indicates that no more wait states are required followed by the TAR to complete the write cycle.
Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
Chip may modify nWRITE and nPDATA in preparation for the next cycle.
If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can
complete when nWAIT goes inactive high.
If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before
changing the state of nWRITE or before nDATASTB goes active. The read can complete once
nWAIT is determined inactive.
The host initiates an I/O read cycle to the selected EPP register.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
The chip tri-states the PData bus and deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
Peripheral drives PData bus valid.
Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase
of the cycle.
Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-
stated.
Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB
or nADDRSTRB. This marks the beginning of the termination phase.
The chip drives the sync that indicates that no more wait states are required and drives valid data
onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.
DATASHEET
100
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet