LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 102

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct
7.10.1 Extended Capabilities Parallel Port
7.10.2 Vocabulary
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
nWRITE
PD<0:7>
INTR
nWAIT
nDATASTB
nRESET
nADDRSTB
PE
SLCT
nERR
EPP read cycles, PCD is required to be a low.
SIGNAL
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost
peripherals Maintains link and data layer separation Permits the use of active output drivers permits the
use of adaptive signal timing Peer-to-peer capability.
The following terms are used in this document:
assert:
forward: Host to Peripheral communication.
reverse:
Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is
always 8 bits.
1
0
These terms may be considered synonymous:
EPP
A high level.
A low level.
9.
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
Address
Strobe
Paper End
Printer
Selected
Status
Error
EPP NAME
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
Peripheral to Host communication
TYPE
I/O
Table 7.2 - EPP Pin Descriptions
O
O
O
O
I
I
I
I
I
DATASHEET
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device
is ready for the next transfer.
This signal is active low. It is used to denote data read or
write operation.
This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
102
EPP DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet