LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 191

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC LPC47M182
Table 11.14 – Power Control/Runtime Register Block Logical Device Configuration Registers
CLOCKI32
Default = 0x00
on VTR POR
INT_G
Default = 0x00
on VCC POR, VTR
POR, HARD
RESET and SOFT
RESET
NAME
INDEX
(R/W)
REG
0xF0
0xF1
R/W
DATASHEET
Bit[0] (CLK32_PRSN)
Bit[1] SPEKEY_EN. This bit is used to turn the logic for
the “wake on specific key” feature on and off. It will
disable the 32kHz clock input to the logic when turned
off. The logic will draw no power when disabled.
Bits[7:2] are reserved
Bit[7:1] Reserved
Bit[0]
Note:
offset 0x1B and 0x1C for configuring Interrupt
Generating Registers.
191
0=32kHz clock is connected to the CLKI32
pin (default)
1=32kHz clock is not connected to the CLKI32
pin (pin is grounded)
1= “Wake on specific key” logic is off
INT_G Enable
See Power Control Block runtime registers at
0 =
(INT_GENx) from affecting the serial IRQ
stream
1 = Enable Interrupt Generating Registers to
drive one or more frames low in the SER IRQ
stream
Disable Interrupt Generating Registers
0= “Wake on specific key” logic is
on (default)
DEFINITION
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)