LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 165

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 10 Runtime Register Block Runtime
SMSC LPC47M182
REGISTER
OFFSET
(HEX)
01-03
05-07
0C
0D
1C
1D
00
04
08
09
0A
0B
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1F
20
21
22
23
24
25
Table 10.1 shows the runtime register summary. The Runtime Register Block runtime registers can only
be accessed when LD_NUM bit in the TEST 7 configuration register is ‘1’. See “Power Control Runtime
Registers” section and “GPIO Runtime Registers” section for description of these registers. Note these
offsets replace the register offsets defined in the Power Control logical device and GPIO logical device
when LD_NUM bit is ‘1’
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Table 10.1 – Runtime Register Block Runtime Registers Summary
PCI RESET
Registers
0xFF
0xFF
0x01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC POR
0x01
0xFF
0xFF
DATASHEET
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VTR POR
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x00
0x00
0x00
0x00
0x00
0x80
0x00
0x01
0x01
0x01
0x01
0x01
0x01
165
-
-
-
-
-
-
-
-
-
-
-
RESET
SOFT
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PME_STS
PME_STS3
PME_STS2
PME_STS1
PME_EN3
PME_EN2
PME_EN1
Reserved – reads return 0
LED
Tach1 LSB
Tach1 MSB
Tach2 LSB
Tach2 MSB
MSC_STS
Force Disk Change
Reserved – reads return 0
GP10
GP11
GP12
GP13
GP14
GP15
Reserved – reads return 0
PME_EN
Reserved – reads return 0
Reserved – reads return 0
Keyboard Scan Code
nIO_PME Register
Floppy Data Rate Select Shadow
UART1 FIFO Control Shadow
Interrupt Generating Register 1
Interrupt Generating Register 2
UART2 FIFO Control Shadow
REGISTER