LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 47

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.4.8
SMSC LPC47M182
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main
Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive
data via the Data Register. It should be read before each byte transferring to or from the data register
except in DMA mode. No delay is required when reading the MSR after a data transfer.
BIT 0 – 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and
overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has
been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Recalibrate commands), this bit is returned to a 0 after the last command byte.
BIT 5 NON-DMA
Reserved, read ‘0’. This part does not support non-DMA mode.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write
is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
RQM
7
DIO
6
Table 6.10 - Default Precompensation Delays
DATA RATE
NON
DMA
500 Kbps
300 Kbps
250 Kbps
5
2 Mbps
1 Mbps
DATASHEET
BUSY
CMD
4
PRECOMPENSATION
47
Reserved Reserved
3
DELAYS
41.67 ns
20.8 ns
125 ns
125 ns
125 ns
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
2
DRV1
BUSY
1
BUSY
DRV0
0