LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 183

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note 1:
11.4
SMSC LPC47M182
0x08
0x09
0x0A
0x0B
Config.
Port
LOGICAL
NUMBER
DEVICE
This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the
OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for
16 bit address qualification.
SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard
resets generated by Vcc or VTR POR (as shown) or the nPCI_RESET signal. These registers are not
affected by soft resets.
Reserved
Reserved
Runtime
Register
Block
Reserved
Config. Port
LOGICAL
DEVICE
n/a
n/a
0x60,0x61
n/a
0x26, 0x27
REGISTER
INDEX
DATASHEET
n/a
n/a
[0x0000:0x0FC0]
on 64-byte boundaries
n/a
0x0100:0x0FFE
On 2 byte boundaries
BASE I/O
(NOTE 1)
183
RANGE
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
n/a
n/a
+00 : PME Status
.
.
.
+3F : Reserved
n/a
See Configuration Register
Summary table. Accessed through
the index and DATA ports located at
the Configuration Port address and
the Configuration Port address +1
respectively.
BASE OFFSETS
FIXED