LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 117

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.23.4 Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop
Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low
for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is
the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising
edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled
mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more
after the rising edge of the Stop Frame’s pulse.
7.23.5 Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported
IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84µS with a 25MHz PCI Bus or 2.88uS with a 33MHz
PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the
secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for
asynchronous buses.
7.23.6 EOI/ISR Read Latency
7.23.7 AC/DC Specification Issue
7.23.8 Reset and Initialization
7.24
SMSC LPC47M182
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could
cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a
system fault.
mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the
same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of
order.
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus
clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI
spec. section 4, sustained tri-state.
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents
while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The
Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default
values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s
and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend,
insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode
first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.
Interrupt Generating Registers
The LPC47M182 contains on-chip Interrupt Generating Registers to enable external software to generate
IRQ1 through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2, are located
at offsets 0x1B and 0x1C, respectively, in the in the Power Control Logical Device, when LD_NUM=0, or
Runtime Register Block Logical Device, when LD_NUM=1, from the base address setting (set at Index
0x60 and 0x61 Configuration Registers). See “Power Control Runtime Registers” and “Runtime Register
Block Runtime Registers” sections.
The host interrupt controller is responsible for ensuring that these latency issues are
DATASHEET
117
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)