LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 146

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.37.1 Selecting the Delay
7.38
Note:
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
Bits 3:2 of the nIO_PME register, (located at offset 16h in the in the Power Control Logical Device, when
LD_NUM=0, or Runtime Register Block Logical Device, when LD_NUM=1), is used to select the delay.
SCK_BJT_GATE Output
The SCK_BJT_GATE requires external pull-up to V_5P0_STBY.
The SCK_BJT_GATE pin is an open drain output that provides the gate signal for SCK_BJT in the S3
power state. This circuit is used for glitch protection on the SCK line when moving in to and out of the S3
power state. This signal is only required for designs utilizing Rambus memory. This output functions
according to the table below. See the figure below for the circuit implementation.
SCK_BJT_GATE
NAME
PWRGD_PLATFORM
(INPUT)
Table 7.41 – SCK_BJT_GATE Truth Table
0
1
Figure 7.12 – PRWGD_PLATFORM Generation
OD8
Table 7.40 – SCK_BJT_GATE Pin
BUFFER
DATASHEET
POWER
WELL
VTR
146
SCK_BJT_GATE (OUTPUT)
Open-Drain Gate Output for the
SCK_BJT_GATE in S3
Hi-Z
0
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet