LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 8

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Figure 7.18 – Latched Backfeed Cut Flowchart .........................................................................................................151
Figure 7.19 – CNR Circuit ..........................................................................................................................................153
Figure 13.1 - Power-Up Timing ..................................................................................................................................200
Figure 13.2 - Input Clock Timing ...............................................................................................................................201
Figure 13.3 - PCI Clock Timing ..................................................................................................................................201
Figure 13.4 - Reset Timing.........................................................................................................................................201
Figure 13.5 - Ouput Timing Measurement Conditions, LPC Signals ..........................................................................202
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals...........................................................................202
Figure 13.7 - I/O Write................................................................................................................................................202
Figure 13.8 - I/O Read ...............................................................................................................................................203
Figure 13.9 – DMA Request Assertion Through NLDRQ ...........................................................................................203
Figure 13.10 – DMA Write (First Byte) .......................................................................................................................203
Figure 13.11 – DMA Read (First Byte) .......................................................................................................................203
Figure 13.12 – Floppy Disk Drive Timing (At Mode Only) ..........................................................................................204
Figure 13.13 – EPP 1.9 Data Or Address Write Cycle ...............................................................................................205
Figure 13.14 – EPP 1.9 Data Or Address Read Cycle...............................................................................................206
Figure 13.15 – EPP 1.7 Data Or Address Write Cycle ...............................................................................................207
Figure 13.16 – EPP 1.7 Data Or Address Read Cycle...............................................................................................207
Figure 13.17 – Parallel Port FIFO Timing...................................................................................................................209
Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................210
Figure 13.19 – ECP Parallel Port Reverse Timing .....................................................................................................211
Figure 13.20 – Setup and Hold Time .........................................................................................................................212
Figure 13.21 – Serial Port Data..................................................................................................................................212
Figure 13.22 – Keyboard/Mouse Receive/Send Data Timing ....................................................................................213
Figure 13.23 – Fan Tachometer Input Timing ............................................................................................................214
Figure 13.24 – Power LED Output Timing .................................................................................................................214
Figure 13.25 – REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY...............215
Figure 13.26 – REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR...............215
Figure 13.27 – REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY ..........216
Figure 13.28 – REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR ..........216
Figure 13.29 – Rise, Fall And Propagation Timings ...................................................................................................217
Figure 13.30 – Resume Reset Sequence ..................................................................................................................219
Figure 14.1 - 128 Pin QFP Package Outline, 14x20x2.7 Body, 3.2MM Footprint ......................................................220
Figure 15.1 – Example XOR Chain Circuitry..............................................................................................................221
List of Tables
Table 3.1 - LPC47M182 Pin Description ......................................................................................................................14
Table 3.2 – Pins with Internal Resistors .......................................................................................................................23
Table 3.3 – Pins that Require External Resistors.........................................................................................................24
Table 3.4 – Default State of Pins..................................................................................................................................25
Table 6.1 – Super I/O Block Logical Device Number and Addresses ..........................................................................33
Table 6.2 - Status, Data and Control Registers............................................................................................................38
Table 6.3 - Internal 2 Drive Decode – Normal ..............................................................................................................43
Table 6.4 - Internal 2 Drive Decode – Drives 0 and 1 Swapped ..................................................................................43
Table 6.5 - Tape Select Bits .........................................................................................................................................44
Table 6.6 - Drive Type ID .............................................................................................................................................44
Table 6.7 - Precompensation Delays ...........................................................................................................................45
Table 6.8 - Data Rates .................................................................................................................................................46
Table 6.9 - DRVDEN Mapping .....................................................................................................................................46
Table 6.10 - Default Precompensation Delays .............................................................................................................47
Table 6.11 - FIFO Service Delay..................................................................................................................................48
Table 6.12 - Status Register 0 .....................................................................................................................................51
Table 6.13 - Status Register 1 .....................................................................................................................................52
Table 6.14 - Status Register 2 .....................................................................................................................................52
Table 6.15 - Status Register 3 .....................................................................................................................................53
Table 6.16 – Description of Command Symbols ..........................................................................................................56
Table 6.17 - Instruction Set ..........................................................................................................................................59
Table 6.18 - Sector Sizes .............................................................................................................................................65
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
8
SMSC LPC47M182
DATASHEET