LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 97

no-image

LPC47M182

Manufacturer Part Number
LPC47M182
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC47M182-NR
Manufacturer:
SMSC
Quantity:
1
Part Number:
LPC47M182-NR
Manufacturer:
SMSC
Quantity:
6 382
Part Number:
LPC47M182-NR
Manufacturer:
SMSC
Quantity:
20 000
Part Number:
LPC47M182-NW
Manufacturer:
LINEAR
Quantity:
1 630
Part Number:
LPC47M182-NW
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LPC47M182-NW
Manufacturer:
SMSC-Pbf
Quantity:
6
Part Number:
LPC47M182-NW
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
LPC47M182-NW
Quantity:
500
Part Number:
LPC47M182E-NW
Manufacturer:
Microchip Technology
Quantity:
10 000
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.4.2
7.4.3
SMSC LPC47M182
Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic O means that no time out error has occurred; a logic 1 means that a time out error has been
detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode
Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is ‘0’, writing a one to this bit clears
the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the
Parallel Port Mode Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is ‘1’, the
TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are
a low level.
BIT 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0
means an error has been detected; a logic 1 means no error has been detected.
BIT 4 SLT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means
the printer is on line; a logic 0 means it is not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a
paper end; a logic 0 indicates the presence of paper.
BIT 6 nACK - ACKNOWLEDGE
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means
that the printer has received a character and can now accept another. A logic 1 means that it is still
processing the last character or has not received the data.
BIT 7 nBUSY - nBUSY
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register.
A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that
it is ready to accept the next character.
CONTROL PORT
ADDRESS OFFSET = 02H
The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized
by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
DATASHEET
97
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

Related parts for LPC47M182