LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 34

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

6.2
6.3
6.3.1
Note: The CLKRUN# signal is not implemented in this part.
6.3.2
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
LAD[3:0]
nLFRAME
nPCI_RESET
nLDRQ
nIO_PME
nLPCPD
SER_IRQ
PCI_CLK
SIGNAL
NAME
I/O Write
I/O Read
DMA Write
DMA Read
Host Processor Interface (LPC)
The host processor communicates with the LPC47M182 through a series of read/write registers via the
LPC interface.
accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
LPC Interface
The following sub-sections specify the implementation of the LPC bus.
LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI
33MHz electrical signal characteristics.
LPC Cycles
The following cycle types are supported by the LPC protocol.
LPC47M182 ignores cycles that it does not support.
I/O
Input
Input
Output
OD
Input
I/O
Input
TYPE
CYCLE TYPE
The port addresses for these registers are shown in Table 6.1. Register access is
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47M182 to request wakeup.
Powerdown Signal. Indicates that the LPC47M182 should prepare for power to be shut
on the LPC interface.
Serial IRQ.
PCI Clock.
DATASHEET
1 Byte
1 Byte
1 Byte
1 Byte
34
DESCRIPTION
TRANSFER SIZE
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet