LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 50

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

6.4.11 CONFIGURATION CONTROL REGISTER (CCR)
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
Model 30 Mode
BITS 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps
after a hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 – 6 UNDEFINED
Always read as a logic “0”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register. This register is located in the Power Control
Logical Device (when LD_NUM=0) or Runtime Register Block Logical Device (when LD_NUM=1)at offset
0x18.
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 – 7 RESERVED
Should be set to a logical “0”
RESET
RESET
COND.
COND.
DSK CHG
N/A
N/A
7
7
0
N/A
6
0
0
6
0
DATASHEET
N/A
5
0
0
5
0
50
N/A
4
0
0
4
0
DMAEN NOPREC DRATE
N/A
3
0
3
0
Advanced I/O Controller with Motherboard GLUE Logic
N/A
2
0
2
0
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
SMSC LPC47M182
0
0
0
0
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