LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 209

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
13.1.7 Output Drivers
Note 1:
SMSC LPC47M182
nSTROBE
NAME
PD<7:0>
t1
t2
t3
t4
t5
t6
when it has data to send. The data must be stable for the specified setup time prior to the falling edge of
PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the
handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets
HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 13.19.
To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals
(Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers
can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as
open-drain), the drivers are dynamically changed from open-drain to push-pull. The timing for the dynamic
driver change is specified in then IEEE
Standard, Rev. 1.14, July 14, 1993,
implemented properly to prevent glitching the outputs.
The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another
data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
BUSY
PDATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
PDATA Hold from nSTROBE Inactive (Note 1)
nSTROBE Active to BUSY Active
BUSY Inactive to nSTROBE Active
BUSY Inactive to PDATA Invalid (Note 1)
DESCRIPTION
Figure 13.17 – Parallel Port FIFO Timing
DATASHEET
t1
available from Microsoft. The dynamic driver change must be
1284 Extended Capabilities Port Protocol and ISA Interface
209
t4
t2
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
MIN
600
600
450
680
80
t3
TYP
t6
MAX
t5
500
UNITS
ns
ns
ns
ns
ns
ns