LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 3

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
Chapter 1
Chapter 2
Chapter 3
3.1
3.2
3.3
3.4
Chapter 4
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Chapter 6
6.1
6.2
6.3
6.4
SMSC LPC47M182
5.3.1
5.5.1
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11
6.4.12
Buffer Name Descriptions ................................................................................................................. 23
Pins With Internal Resistors .............................................................................................................. 23
Pins That Require External Resistors ............................................................................................... 24
Default State of Pins.......................................................................................................................... 25
3 Volt Operation / 5 Volt Tolerance ................................................................................................... 30
VCC Power........................................................................................................................................ 30
VTR Power ........................................................................................................................................ 30
V5P0_STBY Power ........................................................................................................................... 31
32.768 kHz Trickle Clock Input.......................................................................................................... 31
14.318 MHz Clock Input .................................................................................................................... 32
Internal PWRGOOD .......................................................................................................................... 32
Maximum Current Values.................................................................................................................. 32
Power Management Events (PME/SCI)............................................................................................ 32
Super I/O Registers........................................................................................................................... 33
Host Processor Interface (LPC) ........................................................................................................ 34
LPC Interface .................................................................................................................................... 34
Floppy Disk Controller ....................................................................................................................... 38
Trickle Power Functionality.....................................................................................................................31
Indication of 32KHZ Clock ......................................................................................................................31
LPC Interface Signal Definition...............................................................................................................34
LPC Cycles.............................................................................................................................................34
Field Definitions ......................................................................................................................................35
NLFRAME Usage ...................................................................................................................................35
I/O Read and Write Cycles .....................................................................................................................35
DMA Read and Write Cycles ..................................................................................................................35
DMA Protocol .........................................................................................................................................35
POWER MANAGEMENT .......................................................................................................................36
SYNC Protocol .......................................................................................................................................36
FDC Configuration Registers ..................................................................................................................38
FDC Internal Registers ...........................................................................................................................38
STATUS REGISTER A (SRA) ................................................................................................................39
STATUS REGISTER B (SRB) ................................................................................................................40
DIGITAL OUTPUT REGISTER (DOR) ...................................................................................................42
TAPE DRIVE REGISTER (TDR) ............................................................................................................44
DATA RATE SELECT REGISTER (DSR) ..............................................................................................45
MAIN STATUS REGISTER ....................................................................................................................47
DATA REGISTER (FIFO) .......................................................................................................................48
General Description ........................................................................................................... 11
Pin Layout........................................................................................................................... 12
Description of Pin Functions ............................................................................................. 14
Block Diagram.................................................................................................................... 29
Power and Clock Functionality......................................................................................... 30
Functional Description....................................................................................................... 33
I/O and DMA START Fields ................................................................................................................37
LPC TRANSFERS ..............................................................................................................................37
DIGITAL INPUT REGISTER (DIR)......................................................................................................49
CONFIGURATION CONTROL REGISTER (CCR) .............................................................................50
STATUS REGISTER ENCODING ......................................................................................................51
DATASHEET
3
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)