LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 51

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.4.12 STATUS REGISTER ENCODING
SMSC LPC47M182
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in
Model 30 register mode. Unaffected by software reset.
BIT 3 – 7 RESERVED
Should be set to a logical “0”
Table 6.9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is
unaffected by the DOR and the DSR resets.
During the Result Phase of certain commands, the Data Register contains data bytes that give the status
of the command just executed.
BIT NO.
RESET
COND.
7,6
1,0
5
4
3
2
IC
SE
EC
H
DS1,0
SYMBOL
N/A
7
0
N/A
6
0
Interrupt Code 00 - Normal termination of command. The specified
Seek End
Equipment
Check
Head Address The current head address.
Drive Select
Table 6.12 - Status Register 0
NAME
DATASHEET
N/A
5
0
command was properly executed and completed without
error.
01 - Abnormal termination of command.
execution was started, but was not successfully
completed.
10 - Invalid command. The requested command could
not be executed.
11 - Abnormal termination caused by Polling.
The FDC completed a Seek, Relative Seek or
Recalibrate command (used during a Sense Interrupt
Command).
The TRK0 pin failed to become a "1" after:
1. Step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to
Unused. This bit is always "0".
The current selected drive.
51
step outward beyond Track 0.
N/A
4
0
N/A
3
0
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DESCRIPTION
NOPREC DRATE
N/A
2
SEL1
1
1
Command
DRATE
SEL0
0
0