LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 115

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.23.1 Timing Diagrams For SER_IRQ Cycle
7.23.2 SER_IRQ Cycle Control
SMSC LPC47M182
PCI_CLK
SER_IRQ
PCI_CLK
SER_IRQ
Drive Source
Note:
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period
Note:
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
A) Start Frame timing with source sampled a low pulse on IRQ1
There are two modes of operation for the SER_IRQ Start Frame:
1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock,
while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated
without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The
SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop
Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions
which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the
next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks.
This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the
SER_IRQ back high for one clock, then tri-state.
Driver
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
hierarchy in a synchronous bridge design.
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
around clock of the Stop Frame.
S
FRAME
None
IRQ14
R
IRQ1
SL
or
H
T
START
S
Host Controller
START FRAME
IRQ15
H
IRQ15
FRAME
R
1
DATASHEET
T
R
S
IOCHCK#
None
FRAME
T
115
R
IRQ0 FRAME IRQ1 FRAME
T
S
None
I
R
2
STOP FRAME
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
Host Controller
T
STOP
H
S
IRQ1
1
R
R
T
T
NEXT CYCLE
IRQ2 FRAME
S
None
START
R
T
3