LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 126

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.26.2 Keyboard and Mouse PME Generation
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
Bit[4]:
Bit[3]:
These bits are defined as follows:
See the “Configuration” section for a description of this register.
The LPC47M182 sets the associated PME Status bits when the following conditions occur:
These events can cause a PME to be generated if the associated PME Wake Enable register bit and the
global PME_EN bit are set. Refer to the PME Support section for more details on the PME interface logic
and refer to the “Power Control Runtime Registers” and “Runtime Register Block Runtime Registers”
sections for details on the PME Status and Enable registers.
The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC.
The keyboard data and mouse data PMEs can be generated both when the part is powered by VCC, and
when the part is powered by VTR (VCC=0).
When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard
signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is
due to the fact that the normal operation of the 8042 can prevent the system from entering a sleep state or
trigger false PME events. The LPC47M182 has a mode to select the isolation of keyboard and mouse
clock and data signals by hardware when the nLPCPD signal is active and/or when the isolation bits are
set by software. The mode allows the keyboard and mouse data signals to go into the wakeup logic but
block the clock and data signals from the 8042. The mode may be used anytime it is necessary to isolate
the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state. This mode
applies to ANYKEY wakeup from S3, but it does not affect wake from S1. The mode is selected by
ISO_MODE bit in the Keyboard logical device configuration register 0xF0. The ISO_MODE bit is defined
as follows:
Bit[7] ISO_MODE in KRST_GA20 register (0xF0)
0: Mode 1 (default) – Isolate the 8042 in hardware while the nLPCPD signal is active OR when the
Keyboard and Mouse isolation bits are set by software.
1: Mode 2 – Keyboard and mouse isolation bits set by software only. (Note: the input path to the 8042 is
also isolated while the nLPCPD signal is active.)
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Keyboard Logical
Device, Register 0xF0 (KRST_GA20) and are defined below. These bits reset on VTR POR only.
See the SMSC Application Note titled “Using the Enhanced Keyboard and Mouse Wakeup Feature in
SMSC Super I/O Parts” for more information on isolation bits.
MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with
Latched MINT (default), 1=MINT is the latched 8042 MINT.
KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed
with Latched KINT (default), 1=KINT is the latched 8042 KINT.
Keyboard Interrupt
Mouse Interrupt
Active Edge on Keyboard Data Signal (KDAT)
Active Edge on Mouse Data Signal (MDAT)
Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT
signal to the mouse wakeup (PME) logic.
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the
KDAT signal to the keyboard wakeup (PME) logic.
1=block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
1=block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into 8042
DATASHEET
126
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet