LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 101

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.8
7.8.1
7.9
7.10
SMSC LPC47M182
EPP 1.7 Operation
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in
the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is
required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of
the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-
out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3
are set to zero. Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read.
EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or
Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is
inactive high.
Write Sequence of Operation
EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip
inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
The host initiates an I/O write cycle to the selected EPP register.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and
the WRITE signal is valid.
If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts
nWAIT or a time-out occurs.
The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the
internal data bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
1.
2.
3.
4.
5.
6.
7.
8.
The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-
states the PData bus.
The host initiates an I/O read cycle to the selected EPP register.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set
and the nWRITE signal is valid.
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral
deasserts nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the
termination phase of the cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
DATASHEET
101
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)