LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 122

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.25.17 External Clock Signal
7.25.18 Default Reset Conditions
7.25.19 GATEA20 AND KEYBOARD RESET
7.26
7.26.1 Port 92 Register
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
C/D
IBF
OBF
The LPC47M182 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock.
The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to
both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock
signal is not loaded by the chip.
The LPC47M182 has one source of hardware reset: an external reset via the nPCI_RESET pin. Refer to
Table 7.13 for the effect of each type of reset on the internal registers.
The LPC47M182 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated
GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
Port 92 Fast Gatea20 and Keyboard Reset
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register
(Keyboard Logical Device, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
(Command Data)-This bit specifies whether the input data register contains data or a command (0 =
data, 1 = command). During a host data/command write operation, this bit is set to “1” if SA2 = 1 or
reset to “0” if SA2 = 0.
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data
register. Setting this flag activates the LPC47M182 CPU’s nIBF (MIRQ) interrupt if enabled. When
the LPC47M182 CPU reads the input data register (DBB), this bit is automatically reset and the
interrupt is cleared. There is no output pin associated with this internal signal.
(Output Buffer Full) - This flag is set to whenever the LPC47M182 CPU write to the output data
register (DBB). When the host system reads the output data register, this bit is automatically reset.
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values
Host I/F Status Reg
Host I/F Data Reg
DESCRIPTION
MDAT
KDAT
MCLK
KCLK
DATASHEET
N/A: Not Applicable
122
HARDWARE RESET
(nPCI_RESET)
Low
Low
Low
Low
00H
N/A
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet