LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 208

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

13.1
13.1.1 Parallel Port FIFO (Mode 101)
13.1.2 ECP Parallel Port Timing
13.1.3 Forward-Idle
13.1.4 Forward Data Transfer Phase
13.1.5 Reverse-Idle Phase
13.1.6 Reverse Data Transfer Phase
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
ECP PARALLEL PORT TIMING
The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using
DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to
Figure 13.17.
The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter
cable is used then the bandwidth will increase.
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk
(Busy) low.
The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck
and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward
Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel
be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk
(nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior
to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the
handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets
PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 13.18.
The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously
with HostClk (nStrobe).
The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low.
The interface transfers data and commands from the peripheral to the host using an interlocked HostAck
and PeriphClk.
The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte
has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low
DATASHEET
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Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M182
Datasheet