LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 43

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC LPC47M182
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1”
is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the
other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable
the DMA and interrupt functions. This bit is a logic “0” after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will
be cleared to a logic “0”.
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active.
BIT 6 MOTOR ENABLE 2
The MTR2 disk interface output is not supported in the LPC47M182.
BIT 7 MOTOR ENABLE 3
The MTR3 disk interface output is not supported in the LPC47M182.
Bit 5
Bit 5
X
X
1
0
1
0
DIGITAL OUTPUT
DIGITAL OUTPUT
Bit 4
Bit 4
REGISTER
REGISTER
X
X
1
0
1
0
Table 6.4 - Internal 2 Drive Decode – Drives 0 and 1 Swapped
Bit1
Bit1
X
X
0
0
0
0
Table 6.3 - Internal 2 Drive Decode – Normal
Bit 0
Bit 0
0
1
X
0
1
X
DRIVE
DRIVE SELECT OUTPUTS
DRIVE SELECT OUTPUTS
DATASHEET
0
1
nDS1
nDS1
1
0
1
0
1
1
(ACTIVE LOW)
(ACTIVE LOW)
43
nDS0
nDS0
DOR VALUE
0
1
1
1
0
1
1CH
2DH
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
MOTOR ON OUTPUTS
MOTOR ON OUTPUTS
nMTR1
nMTR1
nBIT 5
nBIT 5
nBIT 5
nBIT 4
nBIT 4
nBIT 4
(ACTIVE LOW)
(ACTIVE LOW)
nMTR0
nMTR0
nBIT 4
nBIT 4
nBIT 4
nBIT 5
nBIT 5
nBIT 5