LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 96

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

(1) = Compatible Mode
(3) = High Speed Mode
Note:
7.4
7.4.1
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
CONNECTOR
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
document is available from Microsoft.
IBM XT/AT Compatible, Bi-Directional and EPP Modes
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
HOST
2-9
10
11
12
13
14
15
16
17
1
See section Chapter
3 Description of Pin
PIN NUMBER
Functions.
SMSC
Table 7.1 - Parallel Port Connector
DATASHEET
nSTROBE
PD<0:7>
nACK
BUSY
PE
SLCT
nALF
nERROR
nINITP
nSLCTIN
STANDARD
96
nWrite
PData<0:7>
Intr
nWait
(User Defined)
(User Defined)
nDatastb
(User Defined)
nRESET
nAddrstrb
EPP
Advanced I/O Controller with Motherboard GLUE Logic
nStrobe
PData<0:7>
nAck
PError,
nAckReverse (3)
Select
nAutoFd,
HostAck(3)
nFault (1)
nPeriphRequest (3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
Busy, PeriphAck(3)
ECP
SMSC LPC47M182
Datasheet
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