LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 46

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x19 in the
Power Control Logical Device (when LD_NUM=0) or Runtime Register Block Logical Device (when LD_NUM=1).
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
BIT 6 LOW POWER
A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual low
power mode after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
Separator circuits will be turned off. The controller will come out of manual low power.
DRT1
DRIVE RATE
DT1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
DRT0
DT0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
SEL1
01 = 3-Mode Drive
10 = 2 Meg Tape
DATA RATE
DRVDEN1 (1)
1
0
0
1
1
0
0
1
1
0
0
1
Table 6.9 - DRVDEN Mapping
DRATE0
DRATE0
DRATE0
DRATE1
Table 6.8 - Data Rates
SEL0
DATASHEET
1
0
1
0
1
0
1
0
1
0
1
0
1Meg
1Meg
1Meg
2Meg
MFM
500
300
250
500
500
250
500
250
DATA RATE
DRVDEN0 (1)
46
nDENSEL
DENSEL
DRATE1
DRATE0
250
150
125
250
250
125
250
125
FM
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4/2/1 MB 3.5”
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3-MODE)
PS/2
DENSEL
Advanced I/O Controller with Motherboard GLUE Logic
1
1
0
0
1
1
0
0
1
1
0
0
DRIVE TYPE
DRATE(1)
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SMSC LPC47M182
Datasheet