LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 7

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 10
Chapter 11
11.1
11.2
11.3
11.4
Chapter 12
12.1
12.2
12.3
12.4
Chapter 13
13.1
Chapter 14
Chapter 15
Chapter 16
List of Figures
Figure 2.1 - LPC47M182 Pin Layout ............................................................................................................................12
Figure 4.1 – LPC47M182 Block Diagram.....................................................................................................................29
Figure 7.1 – NKBDRST Circuit...................................................................................................................................124
Figure 7.2 – Keyboard Latch ......................................................................................................................................125
Figure 7.3 – Mouse Latch ..........................................................................................................................................125
Figure 7.4 – GPIO Function Illustration ......................................................................................................................130
Figure 7.5 – Fan Tachometer Input and Clock Source...............................................................................................134
Figure 7.6 – NHD_LED Circuit ...................................................................................................................................136
Figure 7.7 – Example Yellow and Green LED Circuit.................................................................................................137
Figure 7.8 – REF5V Circuit ........................................................................................................................................138
Figure 7.9 – REF5V_STBY ........................................................................................................................................139
Figure 7.10 – VGA DDC Voltage Translation Circuit..................................................................................................142
Figure 7.11 – SMBUS Isolation Circuit.......................................................................................................................144
Figure 7.12 – PRWGD_PLATFORM Generation .......................................................................................................146
Figure 7.13 - SCK_BJT_GATE Circuit .......................................................................................................................147
Figure 7.14– Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................148
Figure 7.15 – Latched Backfeed Cut Power Up Sequence ........................................................................................149
Figure 7.16 – Latched Backfeed Cut Sequence 1......................................................................................................149
Figure 7.17 – Latched Backfeed Cut Sequence 2......................................................................................................150
SMSC LPC47M182
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.1.7
11.1.8
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
System Elements ......................................................................................................................... 167
Chip Level (Global) Control/Configuration Registers[0x00-0x2F]................................................ 174
Logical Device Configuration/Control Registers [0x30-0xFF] ...................................................... 177
SMSC Defined Logical Device Configuration Registers .............................................................. 183
Maximum Guaranteed Ratings .................................................................................................... 192
Operational DC Characteristics ................................................................................................... 192
Standby Power Requirements .....................................................................................................197
Capacitance Values for Pins........................................................................................................ 197
ECP PARALLEL PORT TIMING.................................................................................................. 208
Primary Configuration Address Decoder...........................................................................................167
Entering the Configuration State .......................................................................................................167
Exiting the Configuration State..........................................................................................................167
CONFIGURATION SEQUENCE .......................................................................................................168
Enter Configuration Mode .................................................................................................................168
Configuration Mode...........................................................................................................................168
Exit Configuration Mode....................................................................................................................168
Programming Example......................................................................................................................169
Parallel Port FIFO (Mode 101) ..........................................................................................................208
ECP Parallel Port Timing ..................................................................................................................208
Forward-Idle ......................................................................................................................................208
Forward Data Transfer Phase ...........................................................................................................208
Reverse-Idle Phase...........................................................................................................................208
Reverse Data Transfer Phase...........................................................................................................208
Output Drivers ...................................................................................................................................209
Runtime Register Block Runtime Registers ............................................................... 165
Configuration ................................................................................................................ 167
Electrical Characteristics ............................................................................................. 192
Timing Diagrams .......................................................................................................... 199
Package Outline ............................................................................................................ 220
Board Test Mode........................................................................................................... 221
Reference Documents ................................................................................................... 223
DATASHEET
7
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)