LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 9

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 6.19 - Effects of MT and N Bits ..........................................................................................................................66
Table 6.20 - Skip Bit vs Read Data Command.............................................................................................................66
Table 6.21 - Skip Bit vs. Read Deleted Data Command ..............................................................................................67
Table 6.22 - Result Phase Table..................................................................................................................................67
Table 6.23 - Verify Command Result Phase Table ......................................................................................................69
Table 6.24 - Typical Values for Formatting ..................................................................................................................70
Table 6.25 - Interrupt Identification...............................................................................................................................72
Table 6.26 - Drive Control Delays (ms) ........................................................................................................................73
Table 6.27 - Effects of WGATE and GAP Bits .............................................................................................................77
Table 6.28 – Addressing the Serial Port.......................................................................................................................78
Table 6.29 - Interrupt Control Table .............................................................................................................................82
Table 6.30 - Baud Rates ..............................................................................................................................................89
Table 6.31 - Reset Function Table ...............................................................................................................................90
Table 6.32 - Register Summary for an Individual UART Channel ................................................................................91
Table 7.1 - Parallel Port Connector ..............................................................................................................................96
Table 7.2 - EPP Pin Descriptions ...............................................................................................................................102
Table 7.3 - ECP Pin Descriptions...............................................................................................................................104
Table 7.4 - ECP Register Definitions..........................................................................................................................105
Table 7.5 - Mode Descriptions ...................................................................................................................................105
Table 7.6 - Extended Control Register .......................................................................................................................109
Table 7.7 – Programming for Configuration Register B (Bits 5:3) ..............................................................................109
Table 7.8 – Programming for Configuration Register B (Bits 2:0) ..............................................................................110
Table 7.9 - Channel/Data Commands supported in ECP mode .................................................................................111
Table 7.10 - I/O Address Map ....................................................................................................................................119
Table 7.11 - Host Interface Flags ...............................................................................................................................119
Table 7.12 - Status Register ......................................................................................................................................121
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................122
Table 7.14 – Keyboard Port 92 Register ....................................................................................................................123
Table 7.15 – nA20M Truth Table................................................................................................................................124
Table 7.16 – GPIO Summary.....................................................................................................................................128
Table 7.17 – General Purpose I/O Port Assignments ................................................................................................128
Table 7.18 – GPIO Configuration Summary...............................................................................................................129
Table 7.19 – GPIO Read/Write Behavior ...................................................................................................................130
Table 7.20 – Hard Drive Front Panel Pins..................................................................................................................135
Table 7.21 – nHD_LED Truth Table...........................................................................................................................136
Table 7.22-- LED Pins...............................................................................................................................................136
Table 7.23 - LED Truth Table.....................................................................................................................................137
Table 7.24 – Reference Generation Pins ...................................................................................................................138
Table 7.25 – REF5V...................................................................................................................................................138
Table 7.26 – REF5V_STBY .......................................................................................................................................139
Table 7.27 – nIDE_RSTDRV Pin ...............................................................................................................................140
Table 7.28 – nIDE_RSTDRV Truth Table ..................................................................................................................140
Table 7.29 – nPCIRST_OUT Pins..............................................................................................................................140
Table 7.30 – nPCIRST_OUT and nPCIRST_OUT2 Truth Table................................................................................140
Table 7.31 – Voltage Translation DDC Pins...............................................................................................................140
Table 7.32 – VGA DDCSDA Voltage Translation Logic .............................................................................................141
Table 7.33 – VGA DDCSCL Voltage Translation Logic..............................................................................................142
Table 7.34 – SMBus Isolation Pins ............................................................................................................................143
Table 7.35 – SMB_CLK Isolation Logic......................................................................................................................143
Table 7.36 – SMB_DAT Isolation Logic .....................................................................................................................143
Table 7.37 – nPS_ON, nCPU_PRESENT and nSLP_S3 Pins...................................................................................144
Table 7.38 – nPS_ON Truth Table.............................................................................................................................145
Table 7.39 – PWRGD_PLATFORM Truth Table........................................................................................................145
Table 7.40 – PWRGD_PLATFORM Delay Selection .................................................................................................146
Table 7.41 – SCK_BJT_GATE Pin.............................................................................................................................146
Table 7.42 – SCK_BJT_GATE Truth Table ...............................................................................................................146
Table 7.43 – nBACKFEED_CUT and LATCHED_BF_CUT Pins ...............................................................................147
Table 7.44 – nBACKFEED_CUT Truth Table ............................................................................................................147
Table 7.45 – LATCHED_BF_CUT Truth Table ..........................................................................................................148
Table 7.46 – Latched Backfeed Cut Power Up Sequence Timing .............................................................................149
SMSC LPC47M182
9
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET