LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 55

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.8
6.9
SMSC LPC47M182
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster
servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until
empty (full), then the transfer request goes inactive. The host must be very responsive to the service
request. This is the desired case for use with a “fast” system.
A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a
service request, but results in more frequent service requests.
Non-DMA Mode – Transfers from the FIFO to the Host
This part does not support non-DMA mode.
Non-DMA Mode – Transfers from the Host to the FIFO
This part does not support non-DMA mode.
DMA Mode – Transfers from the FIFO to the Host
The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last byte
of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by
reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by
generating the proper sync for the data transfer.
DMA Mode – Transfers from the Host to the FIFO.
The FDC generates a DMA request cycle when entering the execution phase of the data transfer
commands. The DMA controller must respond by placing data in the FIFO. The DMA request remains
active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has <threshold>
bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more
data is required.
Data Transfer Termination
The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun
and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector
to be transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector,
and the FDC will continue to complete the sector as if a TC cycle was received. The only difference
between these implicit functions and TC cycle is that they return “abnormal termination” result status.
Such status indications can be ignored if they were expected.
Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete
when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the
transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The
host must tolerate this delay.
Result Phase
The generation of the interrupt determines the beginning of the result phase. For each of the commands,
a defined set of result bytes has to be read from the FDC before the result phase is complete. These
bytes of data must be read out for another command to start.
DATASHEET
55
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)