LPC47M182 SMSC Corporation, LPC47M182 Datasheet - Page 154

• Manufacturer Part Number: LPC47M182
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Chapter 8
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
REGISTER
OFFSET
01 – 03
05 – 07
1E-1F
(hex)
0C
0D
1C
1D
00
04
08
09
0A
0B
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
Table 8.1 shows the runtime registers summary in the Power Control logical Device. Table 8.2 shows the
runtime registers description in the Power Control logical device. These runtime registers can only be
accessed when LD_NUM bit in the TEST 7 configuration register is ‘0’ (see Table 11.3). The register
offsets are from the base address programmed in the Power Control logical device.
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Table 8.1 – Power Control Runtime Registers Summary, LD_NUM Bit = 0
PCI Reset
Power Control Runtime Registers
0xFF
0xFF
0x01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC POR
0x01
0xFF
0xFF
DATASHEET
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VTR POR
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x00
0x00
0x00
0x00
0x00
0x80
0x00
154
-
-
-
-
-
-
-
-
-
-
-
RESET
SOFT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Advanced I/O Controller with Motherboard GLUE Logic
PME_STS
Reserved – reads return 0
Reserved – reads return 0
PME_STS3
PME_STS2
PME_STS1
PME_EN3
PME_EN2
PME_EN1
Reserved – reads return 0
LED
Tach1 LSB
Tach1 MSB
Tach2 LSB
Tach2 MSB
MSC_STS
Force Disk Change
Reserved – reads return 0
PME_EN
Reserved – reads return 0
Keyboard Scan Code
nIO_PME Register
Floppy Data Rate Select Shadow
UART1 FIFO Control Shadow
Interrupt Generating Register 1
Interrupt Generating Register 2
UART2 FIFO Control Shadow
REGISTER
SMSC LPC47M182
Datasheet