28478G-18 Mindspeed Technologies, 28478G-18 Datasheet
28478G-18
Specifications of 28478G-18
Related parts for 28478G-18
28478G-18 Summary of contents
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... CN8478/74A/72A/71A Multichannel Synchronous Communications Controller (MUSYCC™) Data Sheet 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Feb. 2008 ...
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... G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information. Revision History Revision Level E Preliminary D October B Advance March 2005 ...
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... Port Interrupt Processor Interface Controller Tx/Rx-BLP Tx/Rx Expanion Bus Interface ® Mindspeed Technologies Distinguishing Features 256-, 128-, 64-, or 32-channel HDLC controller OSI Layer 2 protocol support General purpose HDLC (ISO 3309) X.25 (LAPB) Frame relay (LAPF/ANSI T1.618) ISDN D-channel (LAPD/Q.921) SS7 support ...
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... Expansion Bus (EBUS 3.1 Operation .48 3.1.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.1.2 Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.1.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.1.4 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.1.5 Address Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.1.6 Data Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.1.7 Bus Access Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.1.8 PCI to EBUS Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.1.9 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies iv ...
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... Service Request80 5.2.2.3 Group Configuration Descriptor83 5.2.2.4 Memory Protection Descriptor85 5.2.2.5 Port Configuration Descriptor85 5.2.2.6 Message Length Descriptor86 5.2.2.7 Time Slot Map87 5.2.2.8 Subchannel Map89 5.2.3 Channel Level Descriptors91 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Table of Contents v ...
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... Interrupt Queue Configuration114 6.2.4 Channel Group(s) Configuration114 6.2.5 Service Request Mechanism115 6.2.6 MUSYCC Internal Memory115 6.2.6.1 Memory Operations—Inactive Channels115 6.2.6.2 Memory Operations—Active Channels116 6.3 Channel Operation116 6.3.1 Group Structure117 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Table of Contents vi ...
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... Message Configuration Bits Copy Enable/Disable135 6.4.7 Bit-Level Operation136 6.4.7.1 Transmit137 6.4.7.2 Receive137 6.4.8 HDLC Mode138 6.4.8.1 Transmit Events138 6.4.8.2 Receive Events139 6.4.8.3 Transmit Errors141 6.4.8.4 Receive Errors143 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Table of Contents vii ...
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... Bit Stream Transmission Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 8.4 Bit Stream Storage Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 8.5 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 8.6 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Appendix A: JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 A.1 Instruction Register .180 A.2 BYPASS Register .181 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Table of Contents viii ...
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... Transmit Data Bit Output Value Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69 Figure 5-1. Shared Memory Model Per Channel Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 Figure 5-2. Interrupt Notification To Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110 Figure 7-1. PCI Clock (PCLK) Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-159 Figure 7-2. PCI Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-160 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies ix ...
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... Figure 7-18. Serial Interface Data Delay Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-172 Figure 7-19. 208-Pin Metric Quad Flatpack (MQFP 7-173 Figure 7-20. 208-Pin Plastic Ball Grid Array (PBGA 7-174 Figure A-1. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-181 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies List of Figures x ...
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... Example of 16-Channel without Subchanneling Buffer Allocation (Receive or Transmit 4-68 Table 5-1. MUSYCC Register Map 5-72 Table 5-2. Group Structure Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 Table 5-3. MUSYCC PCI Function Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 Table 5-4. Shared Memory Allocation—Group Descriptors 5-75 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies xi ...
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... Table 6-10. Example—Components of Channel Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126 Table 6-11. Polling Frequency Using a Time Slot Counter Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-133 Table 6-12. Memory Map for Message Configuration Descriptor Table 6-136 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies List of Tables xii ...
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... MUSYCC Byte Transmission Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-176 Table 8-5. Little-Endian Storage Convention (Intel-style 8-176 Table 8-6. Big-Endian Storage Convention (Motorola-style 8-177 Table A-1. IEEE Std. 1149.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-180 Table A-2. JTAG Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-181 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies List of Tables xiii ...
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... Serial Interface 1 Host Interface Serial (PCI) Interface 2 Serial Interface 3 Serial Interface 4 Expansion Bus Interface Serial Interface 5 Serial Interface 6 Serial Interface 7 MUSYCC EBUS ® Mindspeed Technologies Physical Interface 0 Physical Interface 1 Physical Interface 2 Physical Interface 3 Physical Interface 4 Physical Interface 5 Physical Interface 6 Physical Interface 7 1 ...
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... This allows the host processor to concentrate on managing the higher layers of the protocol stack. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies System Description 2 ...
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... Controller Tx/Rx-DMAC Tx/Rx-BLP Serial Interface Channel Group 7 DMA Bit-Level Interrupt Processor Controller Controller Tx/Rx-DMAC Tx/Rx-BLP Boundary Scan and Test Access Expansion Bus Interface ® Mindspeed Technologies System Description RCLK0 RSYNC0 RDAT0 Port ROOF0 Interface TCLK0 Tx/Rx TSYNC0 TDAT0 RCLK1 RSYNC1 RDAT1 ...
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... Channel Group 2 Descriptor Channel Group 1 Descriptor Channel Group 0 Descriptor Tx Channel 31 Message List Tx Channel ... Message List Tx Channel 0 Message List Rx Channel 31 Message List Rx Channel ... Message List Rx Channel 0 Message List System Memory ® Mindspeed Technologies System Description Control Data MPU PHY (Optional) Rx 32-Bit Address and Data ...
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... CN8474A, "NC" pins for Channel Group 4 through 7. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential 1-2 summarize the pin assignments for the CN8478 in the MQFP and PBGA ® Mindspeed Technologies System Description Table 1-4 lists the hardware signal Table 1-4 for pin signal ...
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... VSSo 45 PRST 46 GNT* 47 REQ* 48 AD[31] AD[30 AD[29] AD[28] 51 VGG 52 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential CN8478 ® Mindspeed Technologies System Description 156 VGG 155 EAD[8] 154 EAD[7] 153 VSSo 152 EAD[6] 151 EAD[5] 150 EAD[4] 149 EAD[3] 148 VSSo 147 ...
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... REQ* 48 AD[31] 49 AD[30] 50 AD[29] 51 AD[28] 52 VGG 53 VSS 54 AD[27] 55 VSSo 56 AD[26] 57 AD[25] 58 AD[24] 59 CBE[3]* 60 IDSEL 61 AD[23] 62 AD[22] 63 VDDo 64 VSSo ® Mindspeed Technologies Pin Pin Label Number 65 AD[21] 66 AD[20] 67 VDDi 68 VSS 69 AD[19] 70 AD[18] 71 AD[17] 72 AD[16] 73 VSSo 74 CBE[2]* 75 FRAME* 76 IRDY* 77 VDDc 78 VSS 79 TRDY* 80 DEVSEL* ...
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... EAD[7] 155 EAD[8] 156 VGG 157 VSS 158 EAD[9] 159 EAD[10] 160 EAD[11] 161 EAD[12] 162 EAD[13] ® Mindspeed Technologies Pin Pin Label Number 163 EAD[14] 164 VDDo 165 VSSo 166 EAD[15] 167 EAD[16] 168 EAD[17] 169 EAD[18] 170 EAD[19] ...
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... Pin Pin Label Number 196 HOLD(BR*) 197 HLDA(BG*) 198 BGACK* 199 EBE[3]* 200 EBE[2]* 201 VDDo 202 VSSo 203 EBE[1]* 204 EBE[0]* 205 NC 206 NC 207 ROOF[7] 208 RCLK[7] 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies 9 ...
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... REQ* 48 AD[31] 49 AD[30] 50 AD[29] AD[28] 51 VGG 52 Note(s): An active low signal is denoted by a trailing asterisk (*). 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential CN8474A ® Mindspeed Technologies 156 VGG 155 EAD[8] 154 EAD[7] 153 VSSo 152 EAD[6] 151 EAD[5] 150 EAD[4] 149 EAD[3] ...
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... REQ* 48 AD[31] 49 AD[30] 50 AD[29] 51 AD[28] VGG 52 Note(s): An active low signal is denoted by a trailing asterisk (*). 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential CN8472A ® Mindspeed Technologies 156 VGG 155 EAD[8] 154 EAD[7] 153 VSSo 152 EAD[6] 151 EAD[5] 150 EAD[4] 149 EAD[3] ...
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... REQ* 48 AD[31] 49 AD[30] 50 AD[29] 51 AD[28] VGG 52 Note(s): An active low signal is denoted by a trailing asterisk(*). 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential CN8471A ® Mindspeed Technologies 156 VGG 155 EAD[8] 154 EAD[7] 153 VSSo 152 EAD[6] 151 EAD[5] 150 EAD[4] 149 EAD[3] ...
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... AD[15] AD[23] AD[16] PERR* AD[11] CBE[3]* AD[19] TRDY* CBE[1] AD[21] CBE[2]* STOP* AD[12] IDSEL AD[18] DEVSEL* AD[14] AD[22] FRAME* SERR* AD[10] ® Mindspeed Technologies EAD[16] EAD[10] EAD[12] VSSo EAD[11] VSSo EAD[9] VGG EAD[6] EAD[7] VSSo EAD[8] VSSo EAD[3] EAD[4] EAD[5] EAD[1] ...
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... D5 ROOF[6] D6 VDDo D7 BGACK* D8 EAD[31] D9 VDDc D10 EAD[25] D11 VDDi D12 EAD[15] D13 VSSo D14 EAD[4] D15 EAD[3] D16 EAD[5] ® Mindspeed Technologies Pin Pin Label Number E1 ROOF[2] E2 RSYNC[6] E3 RCLK[6] E4 RDAT[6] E13 EAD[1] E14 TCLK[3] E15 EAD[0] E16 EAD[2] F1 RDAT[2] F2 RSYNC[2] F3 RCLK[2] ...
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... N7 AD[17] N8 VDDc N9 PAR N10 AD[13] N11 VDDo N12 AD[8] N13 VSSo N14 AD[1] N15 AD[0] N16 TM[2] P1 AD[30] P2 AD[31] ® Mindspeed Technologies Pin Pin Label Number P3 VSSo P4 REQ* P5 AD[24] P6 AD[23] P7 AD[20] P8 AD[16] P9 IRDY* P10 PERR* P11 AD[15] P12 AD[11] P13 M66EN ...
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... Pin Pin Label Number T4 AD[25] T5 IDSEL T6 AD[22] T7 AD[18] T8 FRAME* T9 DEVSEL* T10 SERR* T11 AD[14] T12 AD[10] T13 CBE[0]* T14 AD[6] T15 AD[5] T16 VSSo 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies 16 ...
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... AD[15] AD[23] AD[16] PERR* AD[11] CBE[3]* AD[19] TRDY* CBE[1] AD[21] CBE[2]* STOP* AD[12] IDSEL AD[18] DEVSEL* AD[14] AD[22] FRAME* SERR* AD[10] ® Mindspeed Technologies EAD[16] EAD[10] EAD[12] VSSo EAD[11] VSSo EAD[9] VGG EAD[6] EAD[7] VSSo EAD[8] VSSo EAD[3] EAD[4] EAD[5] EAD[1] ...
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... AD[15] AD[23] AD[16] PERR* AD[11] CBE[3]* AD[19] TRDY* CBE[1] AD[21] CBE[2]* STOP* AD[12] IDSEL AD[18] DEVSEL* AD[14] AD[22] FRAME* SERR* AD[10] ® Mindspeed Technologies EAD[16] EAD[10] EAD[12] VSSo EAD[11] VSSo EAD[9] VGG EAD[6] EAD[7] VSSo EAD[8] VSSo EAD[3] EAD[4] EAD[5] EAD[1] ...
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... AD[15] AD[23] AD[16] PERR* AD[11] CBE[3]* AD[19] TRDY* CBE[1] AD[21] CBE[2]* STOP* AD[12] IDSEL AD[18] DEVSEL* AD[14] AD[22] FRAME* SERR* AD[10] ® Mindspeed Technologies EAD[16] EAD[10] EAD[12] VSSo EAD[11] VSSo EAD[9] VGG EAD[6] EAD[7] VSSo EAD[8] VSSo EAD[3] EAD[4] EAD[5] EAD[1] ...
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... Channel Group 1 1 Receive Serial Transmit Serial Channel Group Channel Group 0 0 Boundary Scan Scan Chain Test Signal Test Access Host (PCI) Interface ® Mindspeed Technologies 190 ECLK O Clock (1) EBE[3:0]* O Expansion Bus Byte Enable (2) EAD[31:0] I/O Expansion Bus Address/Data 140 TCLK[7] I ...
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... A pullup is required to sustain the deaserted value. o/d Open drain. All outputs are CMOS drive levels and can be used with CMOS or TTL logic. FOOTNOTE: 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Definition ® Mindspeed Technologies 21 ...
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... EBUS arbitration. t/s O When asserted, MUSYCC acknowledges to the bus arbiter that the bus grant signal was detected and a bus cycle will be sustained by MUSYCC until this signal is deasserted. ® Mindspeed Technologies Definition 22 ...
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... If the flywheel mechanism is used, no other synchronization signal is required, because MUSYCC tracks the start of each subsequent frame. If the flywheel mechanism is not used, a subsequent low-to-high assertion is required to indicate the start of the next frame. See SFALIGN bit field in ® Mindspeed Technologies Definition Table 5-12. Table 5-12. ...
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... MUSYCC tracks the start of each subsequent frame during the OOF period. If the flywheel mechanism is not used, then a subsequent RSYNCx assertion is required to indicate the start of the next frame. See SFALIGN bit field in ® Mindspeed Technologies Definition Table 5-12. Table ...
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... I/O TRDY* asserted indicates the target’s readiness to complete the current data phase. s/t/s I/O STOP* asserted indicates the selected target is requesting the master to stop the current transaction. ® Mindspeed Technologies Definition Command Type 0000b Interrupt Acknowledge 0001b Special Cycle ...
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... MHz). When M66EN is driven high, ECLK is equal to PCLK divided by two (typically 33 MHz). This input has an internal 75 KΩ pull-down resistor for backward compatibility with Rev devices. See for the resistive pull-down current values. ® Mindspeed Technologies Definition Tables 7-3 and 7-4 ...
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... V +/- 5%, the VDDi and VDDo require 3.3 V +/- 5%, and the VGG require 5 V +/- 5%. The recommended power ramp sequence is VDDi and VDDo together, then VDDc — 27 pins are provided for ground DC. 10 VSS (core and input) and 17 VSSo (output). ® Mindspeed Technologies Definition TM[2] 0 Normal Operation. Tie to ground. 1 All outputs three-stated. ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Host Interface Tx Control Device Tx Data Configuration Rx Control Registers Rx Data Interrupts Clock Control PCI Interface Data Interrupt Clock PCI Control Configuration Space (Function 0) Interrupt PCI Configuration Space (Function 1) ® Mindspeed Technologies Serial Interface Local Expansion Data Bus (EBUS) 28 ...
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... Memory Write • Configuration Read • Configuration Write • Memory Read Multiple (treated like Memory Read in slave mode) • Memory Read Line (treated like Memory Read in slave mode) 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Host Interface 29 ...
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... The value of the signal lines AD[10:8] selects the function being addressed. MUSYCC supports Functions 0 and 1 and will not respond if another function is selected. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Don't 3-Bit 6-Bit Care Function Register (1) Number Number ® Mindspeed Technologies Host Interface Figure 2-2 shows Bit Number 2-Bit Type (2) (3) Number 30 ...
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... Header Type MUSYCC Base Address Register (BAR) Max Latency Min Grant (1) Device ID Status Base Code Reserved Header Type EBUS Base Address Register (BAR) Reserved ® Mindspeed Technologies Host Interface 8 0 (1) Vendor ID Command Revision ID LatencyTimer Reserved — Reserved — Interrupt Pin Interrupt Line 8 ...
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... RO The unique vendor identification assigned to the manufacturer. This field always returns the value 14F1h. ® Mindspeed Technologies Host Interface Tables 2-3 through 2-9 define these Description ...
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... Fast Back-to-Back Capable. Read Only. Indicates that when MUSYCC is a target capable of accepting fast back-to-back transactions when the transactions are not to the same agent Unused Indicates the device is 66 MHz capable. This bit is set by Revision C and later devices Unused. ® Mindspeed Technologies Host Interface Description 33 ...
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... If 1, MUSYCC is permitted to act as bus master MUSYCC is disabled from generating PCI accesses Memory space. Access control enables MUSYCC to respond to Function 0 memory space access cycles disables MUSYCC’s response I/O space accesses. MUSYCC does not contain any I/O space registers. ® Mindspeed Technologies Host Interface Description 34 ...
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... MUSYCC can keep the bus after starting the access cycle asserting its FRAME*. The latency timer ensures that MUSYCC has a minimum time slot for it to own the bus, but places an upper limit on how long it will own the bus Unused. ® Mindspeed Technologies Host Interface Description Description 35 ...
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... When appended to bits 31:20, these bits specify bound memory range the only amount of address space that a MUSYCC function can be assigned MUSYCC memory space is not prefetchable MUSYCC can be located anywhere in 32-bit address space This base register is a memory space base register, as opposed to I/O mapped. ® Mindspeed Technologies Host Interface Description 36 ...
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... INTA* for HDLC controller interrupts Communicates interrupt line routing. System initialization software will write a value to this register indicating which host interrupt controller input is connected to MUSYCC’s INTA* pin. Tables 2-10 ® Mindspeed Technologies Host Interface Description Description through 2-16 describe these 37 ...
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... This unique device identification is assigned by the manufacturer. This field always returns the value 847xh where x can depending on the 32, 64, 128, or 256 channel version of the device, respectively. 14F1h RO The unique vendor identification assigned to the manufacturer. This field always returns the value 14F1h. ® Mindspeed Technologies Host Interface Description 38 ...
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... Function 1 as the target MUSYCC will ignore parity errors Unused Memory Space access control enables MUSYCC to respond to Function 1 memory space access cycles disables MUSYCC’s response I/O space accesses. MUSYCC does not contain any I/O space registers. ® Mindspeed Technologies Host Interface Description 39 ...
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... Register Level Programming Interface: Indicates there is nothing special about programming MUSYCC. 01h RO Denotes the revision number of MUSYCC. Rev A = 0Ah, Rev B = 0Bh, Rev C = 0Ch, etc. Reset Type Value 0 RO Unused. 80h RO MUSYCC is a multifunction device with the standard layout of configuration register space Unused. ® Mindspeed Technologies Host Interface Description Description 40 ...
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... Defines which PCI interrupt pin Function 1 uses. 02h means MUSYCC uses pin INTB* for interrupts sourced by devices connected to EBUS Communicates interrupt line routing. System initialization software writes a value to this register indicating which host interrupt controller input is connected to MUSYCC’s INTB* pin. ® Mindspeed Technologies Host Interface Description Description Description 41 ...
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... PAR provides even parity across the AD[31:0] and CBE[3:0]* signal lines. The agent receiving the data must assert PERR detects a parity error, provided its Parity Error Response enable bit is set. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Host Interface 42 ...
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... Arbitration latency is also affected by the loading of the system and how efficiently the bus is being utilized. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Host Interface 43 ...
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... Host asserts FRAME* to start access cycle. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential k 1 – ∑ ( Latency Total Bus Activity These 2 clock cycles are the arbitration latency that becomes 0 if the bus was not idle. ® Mindspeed Technologies Host Interface ) Table 2-17 provides an 44 ...
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... PCI clock cycles per dword 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Bus Activity x 8 clock cycles is how long the host will need the bus to execute n data ® Mindspeed Technologies Host Interface 45 ...
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... Therefore, for two MUSYCC's and one host, a host would be sufficient; that is, 260 cycles – 24) – 8 cycles = 204 clock cycles. Rounding for granularity equals 200 cycles. On reset, the value of the latency timers are reset to 0. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Host Interface 46 ...
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... Interrupt 8478_007 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Figures 3-1 EBUS Interface Regenerated Clock and Inverted Address/Data Control Bus Bus Arbitration Arbiter EINT* ® Mindspeed Technologies and 3-2 illustrate block diagrams Local Expansion Bus MPU Intel Motorola T1/E1 Framer Bt8370 47 ...
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... MUSYCC asserts a PCI target disconnect. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Clock Address/Data EBUS Control Interface EINT* Table 2-14, Register 4, Address Table 2-4, Register 1, Address ® Mindspeed Technologies Expansion Bus (EBUS) Local RAM Downloadable ROM Peripheral Devices 10h, and listed 04h). 48 ...
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... YYYYYYYYYYYYYYYYYY Lower 20 Bits AD[19:2] transferred from PCI Bus to EAD[17:0] on the EBUS. Byte addressing with bits 19 and 18 always 0 during address phase. ® Mindspeed Technologies Expansion Bus (EBUS) 0 Bit Number 0 Bit Number Table 5-6). In the disabled state, the 49 ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Table 5-6, Global Configuration Descriptor). The value specifies the Descriptor). The value specifies the additional for more details. and Figure 7-14, EBUS Write/Read Transactions, Motorola- ® Mindspeed Technologies Expansion Bus (EBUS) Table 2- Section Section 7.2.4 for more details. Table 5- Figure 7- ...
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... Asserted high by bus arbiter in response to HOLD signal assertion. Remains asserted until after the HOLD signal is deasserted. If the EBUS is connected and there are no bus arbiters on the EBUS, this signal must be asserted high at all times. ® Mindspeed Technologies Expansion Bus (EBUS) Table 5-6, Global Interpretation ...
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... Asserted low by MUSYCC when it detects BGACK* currently deasserted. As this signal is asserted, MUSYCC begins the EBUS access cycle. After the cycle is finished, this signal is deasserted indicating to the bus arbiter that MUSYCC has released the EBUS. Figure 7-13, EBUS Write/Read ® Mindspeed Technologies Expansion Bus (EBUS) Interpretation Figure 7-14, EBUS Write/Read 52 ...
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... EAD[15:8] EAD[7:0] EAD[8:0] Data Addr Data Addr CN8370 CN8370 CS* CS* EAD9 Device 0,4 dev 0,4 EBE[0]* Chip EBE[1]* Select Logic EBE[2]* EBE[3]* ® Mindspeed Technologies Expansion Bus (EBUS) Data Addr Data Addr CN8370 CN8370 CS* CS* Device 1,5 Device 2,6 Device 3,7 53 ...
Page 67
... Preliminary Information / Mindspeed Proprietary and Confidential Data Addr Data Addr Data Addr 2xCN8370 2xCN8370 2xCN8370 CS* CS* CS* Dev 0 Dev 1 Dev 2 Dev 0, Bank 0 Control Dev 0, Bank 1 Dev 0, Bank 2 Dev 0, Bank 3 Dev 0, Bank 4 ® Mindspeed Technologies Expansion Bus (EBUS Data Addr 2xCN8370 CS* Dev 3 54 ...
Page 68
... EBUS Connection, Multiplexed Address/Data, 8 Framers, No MPU EAD[8:0] EINT* AS*, RWR*, DS*, ECLK Control Lines EAD[10:9]* ALE EBE[0] 8478_012 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Data Addr Data Addr 2xCN8370 2xCN8370 CS* CS* 2:4 Decoder ® Mindspeed Technologies Expansion Bus (EBUS) Data Addr Data Addr 2xCN8370 2xCN8370 CS* CS* 55 ...
Page 69
... Preliminary Information / Mindspeed Proprietary and Confidential Serial Interface Channel Group DMAC Bit Level Processor Interface Rx Event Interrupt Controller Tx Event Tx Bit Level Tx DMAC Processor Interface Definitions). The SERI is responsible for ® Mindspeed Technologies Clock Rx Synchronization Port Data Out-of-Frame Status Clock Tx Port Synchronization Data 56 ...
Page 70
... Preliminary Information / Mindspeed Proprietary and Confidential Bits per Frame 193 Single frame bit, followed by 24 time slots, numbered TS0–TS23. 256 32 time slots, numbered TS0–TS31. 512 64 time slots, numbered TS0–TS63. ® Mindspeed Technologies Serial Interface Table 5-12, Port Configuration Description 57 ...
Page 71
... Bits per Frame 1024 128 time slots, numbered TS0–TS127. Nx8 N time slots, numbered TS0–TSN-1. (1 ≤ N ≤ 128) (Table ® Mindspeed Technologies Serial Interface Description s (256 bits x (1 second / 8.192 x µ s frame recurrence is µ Table 5-15, Time Slot 5-17), enable and assign a time slot ...
Page 72
... Also, in Nx64 mode, the TSYNC must precede the output of bit 0 of the frame by four line clock periods. Figures 4-2 through 4-4 illustrate the timing relationships between the data and the synchronization signal for various modes of operation. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Serial Interface (Table 5- 59 ...
Page 73
... In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on a rising clock edge configuration (d), synchronization and data signals are sampled or latched on a falling clock edge. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential 6 7 F-bit F-bit F-bit F-bit F-bit F-bit F-bit F-bit ® Mindspeed Technologies Serial Interface ...
Page 74
... In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on a rising clock edge. 11. In configuration (d), synchronization and data signals are sampled or latched on a falling clock edge. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Serial Interface ...
Page 75
... In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on a rising clock edge. 11. In configuration (d), synchronization and data signals are sampled or latched on a falling clock edge. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Serial Interface ...
Page 76
... Two frame synchronization events after deassertion of ROOF is detected, MUSYCC generates an interrupt descriptor with the Frame Recovery (FREC) interrupt encoding if the interrupt is not masked (as indicated in Table 5-10, Group Configuration 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Descriptor). ® Mindspeed Technologies Serial Interface 63 ...
Page 77
... Channel Group Processor 0 Channel Group Processor 1 Channel Group Processor 2 Channel Group Processor 3 Channel Group Processor 4 Channel Group Processor 5 Channel Group Processor 6 Channel Group Processor 7 ® Mindspeed Technologies Serial Interface Serial Port 0 Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4 Serial Port 5 Serial Port 6 ...
Page 78
... Additional Data Buffer if No Subchanneling) Time Slot Map Total 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Descriptor). The connection between the serial port and the physical ® Mindspeed Technologies Serial Interface Table 4-2 (Table 5-18, Channel Figures 4-6 Transmit Receive ...
Page 79
... FIFO BLP Data Data 1/2 FIFO Internal Data Buffer Control 1/2 FIFO BLP Data Data 1/2 FIFO Internal Data Buffer ® Mindspeed Technologies Serial Interface Shared DMAC Memory PCI Bus Shared DMAC Memory PCI Bus Table 4-2 specifies 64 dwords of internal ...
Page 80
... Fixed Data Buffer ... 31 Table 4-4, for 32 channels without subchannel buffer allocation. Within Channel Descriptor BUFFLOC (dword Offset from Start of Fixed Data Buffer ... 62 ® Mindspeed Technologies Serial Interface Table 4-3 lists the subchannel buffer (1) BUFFLEN ... (2) 0 ÷ ÷ Number of Channels) 2]–1. (1) BUFFLEN ...
Page 81
... PCI bus, and conclude the transfer by releasing the PCI bus. MUSYCC transfers data autonomously and always attempts to burst data from the PCI. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Within Channel Descriptor BUFFLOC (dword Offset from Start of Fixed Data Buffer ... 60 ® Mindspeed Technologies Serial Interface (1) BUFFLEN ... (2) 3 ÷ ÷ Number of Channels) 2]–1. ...
Page 82
... Port Configuration if ( TRANSMITTER_NOT_ENABLED ) TDAT <= three-state else if ( CHANNEL_IS_MAPPED ) if ( CHANNEL_IS_ACTIVATED ) TDAT = BLP_OUTPUT else TDAT = `logic 1' else if ( THREE_STATE_OUTPUT ) TDAT = three-state else TDAT = `logic 1' Table 5-10, Group Configuration Table 5-14, Transmit or Receive Time Slot ® Mindspeed Technologies Serial Interface Descriptor). Figure 4-8 (1) (2) (3) (4) (5) Descriptor.) Map.) 69 ...
Page 83
... Different versions of MUSYCC support different numbers of channel groups. The host allocates shared memory regions to configure and control each group. Figure 5-1 illustrates the memory model used by MUSYCC for control and data structures required for each supported channel group. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies 70 ...
Page 84
... Next Message Pointer Buffer Descriptor Data Buffer Pointer Next Message Pointer Buffer Descriptor Data Buffer Pointer Next Message Pointer * See Table 5-19 for structure of Message Descriptor. ® Mindspeed Technologies Memory Organization Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer 71 ...
Page 85
... Mindspeed Technologies Memory Organization 10h). Devices connected to the EBUS 10h). Once a base address 2000h 2800h 3000h 3800h 2008h 2808h 3008h 3808h 2200h 2A00h ...
Page 86
... The remaining locations have a corresponding register within MUSYCC. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Group (Byte Offset from Base Address Register 00640h 00644h Table 5-1) are located exclusively within MUSYCC. Table 5-2, are pointer locations exclusive to shared ® Mindspeed Technologies Memory Organization ...
Page 87
... Total Space Required Start Address 0240 0000h 0340 0000h ® Mindspeed Technologies Memory Organization Length (Bytes) 128 128 128 128 128 256 128 128 256 128 1564 ...
Page 88
... Table ® Mindspeed Technologies Memory Organization Length 1,564 bytes 1,564 bytes 1,564 bytes 1,564 bytes 1,564 bytes 1,564 bytes 1,564 bytes 1,564 bytes 5-1 ...
Page 89
... Message Descriptor • Buffer Descriptor • Buffer Status Descriptor • Next Message Pointer • Data Buffer Pointer • Message Descriptor Handling 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Section 5.2.1) Section 5.2.2) Section 5.2.3) Section 5.2.4) ® Mindspeed Technologies Memory Organization 76 ...
Page 90
... Copying the Channel Group 0 Global Configuration Descriptor to all other supported Channel Group Descriptors and requesting a global initialization service request operation for any supported channel groups. The components and their descriptions are listed in 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Section 5.2.5) Table 5-6. ® Mindspeed Technologies Memory Organization 77 ...
Page 91
... ELAPSE+1 number of ECLK periods. The control lines RD* and WR* (Intel) or DS* and R/ WR* (Motorola) indicate that the data bits have had the desired setup time. INTA interrupt enabled. INTA interrupt disabled. INTB interrupt enabled. INTB interrupt disabled. ® Mindspeed Technologies Memory Organization 78 ...
Page 92
... Reserved. Table 5-7. Description Dual Address Cycle Base Pointer. A 32-bit base register when non-0 causes all MUSYCC master operations (read/write) to use PCI Dual Address Cycle. The value in this register would be the upper 32-bits of the 64-bit addressing. ® Mindspeed Technologies Memory Organization 79 ...
Page 93
... These 21 bits are appended with form block-aligned 32-bit address pointing to the first dword of the channel group structure for Channel Group x. These 11 bits appended to GBASE ensure 2 kB block alignment. Table 5-9 lists the bit fields and their descriptions of ® Mindspeed Technologies Memory Organization Map. Table 5-8. 80 ...
Page 94
... Subchannel Map Channel Configuration Descriptor Group Configuration Descriptor Memory Protection Descriptor Message Length Descriptor Port Configuration Descriptor This initialization must be performed by the host driver for each group and each direction immediately following any reset or global initialization. ® Mindspeed Technologies Memory Organization (1) 81 ...
Page 95
... Read Subchannel Map. For this group and specified direction, read the Subchannel Map Read Channel Configuration Table. For this group and specified direction, read the Channel (1) Configuration Table . Reserved. Reserved. Receive direction. Transmit direction. Channel number. ® Mindspeed Technologies Memory Organization ( ...
Page 96
... Memory Protection Violation Action. Reset Group memory protection violation error, group reset is performed result, all 32 channels are deactivated in both receive and transmit directions. Memory Protection Violation Action. Deactivate Channel memory protection violation error, only the channel being serviced during violation is deactivated in both receive and transmit directions. ® Mindspeed Technologies Memory Organization 83 ...
Page 97
... Receiver Enabled. Logically allows all channels with time slot enable bits set to start processing data. This logical, channel-group-wide state does not affect the bit values in any time slot map. ® Mindspeed Technologies Memory Organization 84 ...
Page 98
... Time Slot Map, the transmitter outputs a logic 1 on the output data signal. Receiver Out of Frame—Falling Edge. ROOF input sampled in on falling edge of RCLK. Receiver Out of Frame—Rising Edge. Receiver Frame Synchronization—Falling Edge. RSYNC input sampled in on falling edge of RCLK. Receiver Frame Synchronization—Rising Edge. ® Mindspeed Technologies Memory Organization 85 ...
Page 99
... Mode—64 time slots and E1 signaling. 4xE1 Mode—128 time slots and E1 signaling. Nx64 Mode. Frame synchronization flywheel disabled. COFA detection disabled. Every synchronization signal assertion resets time slot counter to zero. Reserved. Descriptor) selects which, if any, register is used ® Mindspeed Technologies Memory Organization 86 ...
Page 100
... Valid values for the register range from 1 to 4094 depending on FCS16 or FCS32. Reserved. Defines a limit for the maximum number of octets allowed in a received HDLC message. Valid values for the register range from 1 to 4094 depending on FCS16 or FCS32. ® Mindspeed Technologies Memory Organization 87 ...
Page 101
... Time Slot Enabled. 64 kbps mode. Time Slot Enabled. 56 kbps mode. Time Slot Enabled. Subchannel mode w/o first bit. Time Slot Enabled. Subchannel mode w/ first bit. Channel number assigned to this time slot. ® Mindspeed Technologies Memory Organization lists the value and description of each LSB TS01 TS00 ...
Page 102
... Time Slot Disabled. Default. Reserved. Time Slot Enabled. 64 kbps mode. Time Slot Enabled. 56 kbps mode. Time Slot Enabled. Subchannel mode w/o first bit. Time Slot Enabled. Subchannel mode w/ first bit. Channel number assigned to this time slot. ® Mindspeed Technologies Memory Organization 89 ...
Page 103
... Channel number assigned to this bit. 0 Bit disabled. 1 Bit enabled. 0 Reserved. 0–31 Channel number assigned to this bit. ® Mindspeed Technologies Memory Organization lists the value and description of LSB Ch0, Bit 1 Unused Ch0, Bit 5 Ch0, Bit 4 Ch1, Bit 1 Unused Ch1, Bit 5 Ch1, Bit 4 ...
Page 104
... Internal Data Buffer Length. Number of internal FIFO data buffer locations allocated to this channel and direction equals 2 x (BUFFLEN+1) dwords. 0 End Of Padfill Interrupt disabled. Transmit Only. After outputting last padfill code, do not generate interrupt indicating condition. 1 End of Padfill Interrupt enabled. 0 TRANSPARENT 1 SS7-HDLC-FCS16 2 HDLC-FCS16 3 HDLC-FCS32 Reserved. ® Mindspeed Technologies Memory Organization Description 91 ...
Page 105
... FCS error, message alignment error, or abort condition, this bit generates interrupt to indicate condition order for MSKMSG=1 to disable all interrupts (LNG, FCS, ALIGN) the MSKEOM must be set (i.e., 1). 0 EOM Interrupt enabled. Receive and Transmit. Interrupt generated when end of message detected. 1 EOM Interrupt disabled. ® Mindspeed Technologies Memory Organization Description 92 ...
Page 106
... MUSYCC. ONR—Interrupts enabled. Receive and Transmit. Interrupt generated where message pointer/descriptor is not available to MUSYCC where is expected. (Refer to 31, Interrupt Descriptor.) 1 BUFF—Interrupts disabled. ONR—Interrupts disabled. 0 Reserved. Field Name TOTAL ® Mindspeed Technologies Memory Organization Description Figure 5- dwords Bytes ...
Page 107
... Head Pointer The head pointer points to the first message descriptor in a list of descriptors assigned to a channel’s transmitter or receiver. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Memory Organization 94 ...
Page 108
... These 30 bits are appended with 00b to form a dword-aligned 32-bit address. This address points to the first Message Descriptor in a list of descriptors. Ensures dword alignment. Description These 30 bits are appended with 00b to form a dword-aligned 32-bit address. This word pointer points to the first dword of a Message Descriptor. Ensures dword alignment. ® Mindspeed Technologies Memory Organization 95 ...
Page 109
... If PADCNT = 2 and for example, MUSYCC outputs the bit pattern 7Eh..FFh..FFh..7Eh. There is no indication by MUSYCC if more than PADCNT number of idle codes are inserted. ® Mindspeed Technologies Memory Organization 96 ...
Page 110
... EOB interrupt is not generated. End of Buffer Interrupt enabled. Reserved. Buffer Length. Actual number of received data octets might be less than this. This number indicates how many will fit into data buffer. The buffer length should not exceed 8 k. ® Mindspeed Technologies Memory Organization 97 ...
Page 111
... End of Message Indicator. The last octet for this message is not in this buffer. End of Message indicator. The last octet for this data message is in this buffer either because a valid closing flag (7Eh) was detected or the receiver terminated due to an error condition. Reserved. ® Mindspeed Technologies Memory Organization 98 ...
Page 112
... Channel resumes scanning for HDLC flags or idle codes. Reserved. Reserved. Received Octets. These 30 bits are appended with 00b to form a dword-aligned 32-bit address. This address points to the next message descriptor in the list. 0 Ensures dword alignment. ® Mindspeed Technologies Memory Organization Description Description 99 ...
Page 113
... MUSYCC. Tables 5-28 through 5-30 list the details of the Interrupt Queue Descriptor. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Description The 32-bit address in this descriptor serves as a byte pointer to the first octet of a data buffer. ® Mindspeed Technologies Memory Organization 100 ...
Page 114
... This 15-bit number specifies the length of the Interrupt Queue buffer in dwords. The maximum size for an interrupt queue is 32,768 dwords. This is a 0-based number. A value of 1 indicates the queue length is 2 descriptors long, the required minimum. ® Mindspeed Technologies Memory Organization dwords Octets ...
Page 115
... In the list below, a single event can combine with a single error within the same interrupt descriptor: • Events: • EOB • EOM • Errors: • BUFF • COFA • ONR • OOF • FCS • ALIGN • ABT 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Memory Organization 102 ...
Page 116
... GRP[1:0] 0–3 — 28:24 CH[4:0] 0–31 — 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential — Receive. Transmit. — Least significant 2 bits of the Group Number. The most significant group number is defined in bit 14. — Channel Number. ® Mindspeed Technologies Memory Organization Description 103 ...
Page 117
... V SS7 SUERM Octet Count Decrement. Generated when in SS7 mode and Signal Unit Error Rate Monitor counter decrements SS7 Filtered Message. Generated when in SS7 mode and just-received message is identical to one previous message. The current message is not written to shared memory. — Reserved. ® Mindspeed Technologies Memory Organization Description (1) (1) 104 ...
Page 118
... Memory Protection Descriptor. The memory access is inhibited. — Reserved. ( Out of Frame. Generated when serial port is configured in channelized mode, and receiver-out-of-frame (ROOF) input signal assertion is detected. ® Mindspeed Technologies Memory Organization Description 105 ...
Page 119
... The integrity of the descriptor being overwritten is maintained. ® Mindspeed Technologies Memory Organization Description (3) 106 ...
Page 120
... The host can read this value to get the location of the first unserviced descriptor in the queue. As the queue is circular, care must be taken to ensure roll-over cases at beginning and end of queue. The host must update this field with the value of the next available entry in the Interrupt Queue after processing interrupts. ® Mindspeed Technologies Memory Organization Description 107 ...
Page 121
... Interrupt Queue Not Full—shared memory. (1) Interrupt Queue Full—shared memory. Interrupt Count. 15-bit value indicates the number of interrupts pushed into the Interrupt Queue since the last reading of the Interrupt Status Descriptor. All writes to this bit field register are ignored. ® Mindspeed Technologies Memory Organization 108 ...
Page 122
... As MUSYCC detects EINT* assertion, MUSYCC asserts the INTB* towards the host as long as the EINT* remains asserted. The Figure 5-2 illustrates the operation of EINT*. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Memory Organization 109 ...
Page 123
... External Logic Device on EBUS Drives Interrupt Line 8478_022 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential MUSYCC EINT* INTB* INTA* Internal Logic Unserviced Interrupt Descriptors in the Interrupt Queue ® Mindspeed Technologies Memory Organization Host Interrupt Logic Interrupt Logic Memory Interrupt Queue 110 ...
Page 124
... A Soft Chip Reset (SCR device-wide reset without the host interface’s PCI state being reset. Serial interface operations and EBUS operations are stopped. The soft chip reset state is entered in one of two ways: • result of the PCI reset • result of a soft chip reset service request 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies 111 ...
Page 125
... When a soft group reset is requested by the host, the service request mechanism is used. Normally, every service request is acknowledged by MUSYCC with a SACK Interrupt Descriptor. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 112 ...
Page 126
... Read PCI configuration space (Device Identification, Vendor Identification, Class Code, and Revision Identification). • Allocate 1 MB system memory range and assign the Base Address register using this memory range. • Allow fast back-to-back transactions. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 113 ...
Page 127
... Table 5-13, Message Length Descriptor • Table 5-14, Transmit or Receive Time Slot Map • Table 5-16, Transmit or Receive Subchannel Map • Table 5-18, Channel Configuration Descriptor 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Descriptor). Table 5-28, Interrupt Queue ® Mindspeed Technologies Basic Operation Descriptor). 114 ...
Page 128
... Read operations to invalid (unsupported to reserved) addresses or write-only registers return all 1s. Write operations to invalid (unsupported or reserved) addresses or read-only register bits result in the write to that bit location being ignored. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential (transmit or receive) ® Mindspeed Technologies Basic Operation 115 ...
Page 129
... No SS7 functions. • Idle Code = 7Eh. • Pad Fill Count = 0. • C-Language support. • Each section below builds on the previous sections. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Table 5-3, MUSYCC PCI Function Memory ® Mindspeed Technologies Basic Operation Allocation. 116 ...
Page 130
... GroupStr0; /* one per supported group */ /* fixed descriptor offsets into the group structure */ #define GROUP_BASE_OFFSET...............0x00000000 #define DUAL_ADDRESS_CYCLE_BASE_OFFSET..0x00000004 #define SERVICE_REQUEST_OFFSET..........0x00000008 #define INTERRUPT_STATUS_OFFSET.........0x0000000C #define TX_time slot_MAP_OFFSET..........0x00000200 #define TX_SUBCHANNEL_MAP_OFFSET........0x00000280 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 117 ...
Page 131
... MPU control - assume EBUS is not used and default values are fine */ /* PORTMAP = 0, PORT 0 mapped to CHANNEL GROUP 0 */ GroupStr0.GlobalConfigDescr = 0x00000000; 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Table 6-1. Component of Descriptor ® Mindspeed Technologies Basic Operation Value of Components Return pointer from “malloc ( )” adjusted boundary. 118 ...
Page 132
... EBUS clock output disabled Motorola-style protocol supported Don’t care Don’t care. Use 0 where the mapping is defined as: Port 0 -> Channel Group 0 Port 1 -> Channel Group 1 Port 2 -> Channel Group 2 Port 3 -> Channel Group 3 ® Mindspeed Technologies Basic Operation 6-2. 119 ...
Page 133
... MUSYCC register - or - use a service request */ *(MUSYCC_FUNC_0_BAR + GROUP_CONFIG_DESCR_OFFSET) = GroupStr0.GroupConfigDescr; 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Table 6-3. IQPTR pIntQueue, provided by memory allocation functions and adjusted to be dword bound IQLEN IntQueueLen, specified by #define (0-based) ® Mindspeed Technologies Basic Operation Value of Components 120 ...
Page 134
... Message configuration bits copy enabled not mask COFA interrupt not mask OOF interrupt OOF detection, continue processing channel 0 = Subchanneling enabled 1 = Transmitter enabled 1 = Receiver enabled Table Component of Descriptor PROTENBL 0 = Memory protection disabled ® Mindspeed Technologies Basic Operation 6-4. Value of Components 6-5. Value of Components 121 ...
Page 135
... Three-state output when transmitter enabled and time slot is not mapped 0 = Active edge of signals is falling edge channel with E1 signalling Table 6-7. Component of Descriptor 0x200, register 2 to 512 octets 0x400, register 1 to 1024 octets ® Mindspeed Technologies Basic Operation Value of Components Value of Components 122 ...
Page 136
... Table 6- Time slot enabled w/ 64 kbps mode 2 = Logical channel Time slot enabled w/ 64 kbps 2 = Logical channel Time slot enables subchannel mode w/ first bit 1 = Logical channel Time slot enabled w/ 64 kbps mode 0 = Logical channel 0 ® Mindspeed Technologies Basic Operation Value of Components 123 ...
Page 137
... Bit 0 not assigned here, see Time Slot Map 0 = Bit 0 not assigned here see Time Slot Map 0 = Bit 7 disabled 0 = Don’t care 0 = Bit 6 disabled 0 = Don’t care 0 = Bit 5 disabled 0 = Don’t care 0 = Bit 4 disabled 0 = Don’t care ® Mindspeed Technologies Basic Operation Value of Components 124 ...
Page 138
... GroupStr0.TxChannelConfigDescr[2] = 0x02002000; /* either write directly into MUSYCC register - or - use a service request */ *(MUSYCC_FUNC_0_BAR + TX_CHANNEL_CONFIG_DESCR_OFFSET +0) = GroupStr0.TxChannelConfigDescr[0]; *(MUSYCC_FUNC_0_BAR + TX_CHANNEL_CONFIG_DESCR_OFFSET +1) = GroupStr0.TxChannelConfigDescr[1]; *(MUSYCC_FUNC_0_BAR + TX_CHANNEL_CONFIG_DESCR_OFFSET +2) = GroupStr0.TxChannelConfigDescr[2]; 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 125 ...
Page 139
... Data inversion disabled 0 = Total FIFO = (0+1)* dwords 0 = End-of-padfill interrupt disabled 2 = HDLC w/ 16-bit For logical channel 0 application 2 = For logical channel 1 application 0 = For logical channel 2 application 0 = FCS transfer normal 0 = Interrupt masking disabled therefore enabling these interrupts ® Mindspeed Technologies Basic Operation 6-10. 126 ...
Page 140
... MSG_DESCR *pTxMsgDescr[4]; DATA_BUFFER *pDataBuf[4]; /* link the message descriptors together. Terminate the message list assigning the “next” pointer in the last descriptor to point to the last */ /* descriptor itself */ pTxMsgDescr[0]->pNextMsgDescr = pTxMsgDescr[1]; 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 127 ...
Page 141
... Channel Activation is an asynchronous command from the host interface to a transmit or receive section of a channel to jump to a new message. Message Descriptors in shared memory describe the attributes of the new 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 128 ...
Page 142
... If INHRBSD = 0 (i.e., MUSYCC is allowed to overwrite Buffer Descriptor with a Buffer Status Descriptor), the address of the Buffer Descriptor is stored in the Message Pointer slot in shared memory. After current message is completely processed, MUSYCC reads in Next Message Pointer and overwrites Buffer Descriptor 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 129 ...
Page 143
... TRITX in the Port Configuration Descriptor. Data transfers from shared memory are halted. 3. The channel direction remains in the suspended state until the channel is activated. The current channel direction configuration is maintained. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 130 ...
Page 144
... Each serial port frame carries stream data from one or more packetized HDLC or unpacketized Transparent mode channels. Although channels are mapped to specific time slots within the serial port frame, each channel's data 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 131 ...
Page 145
... MHz data stream, the counter is incremented. When the counter rolls over Beginning of Frame is declared. At 2.048 MHz, 256 bits represents 125 ms. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 132 ...
Page 146
... Preliminary Information / Mindspeed Proprietary and Confidential Table 6-11 Poll Throttle Value (Multiples of Frames) Bits Per Frame 0 (x1) 125 µs 192 125 µs 256 125 µs 512 125 µs 1024 ® Mindspeed Technologies Basic Operation lists the various polling frequencies and 1 (x16) 2 (x32) 3 (x64 ...
Page 147
... Configuration Descriptor and include the specifications for the following: • Idle Code specification, IC • Inter-message Pad Fill Enable, PADEN • Inter-message Pad Fill Count, PADCNT • Repeat Message Transmission, REPEAT 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 134 ...
Page 148
... To write new configuration bits into the Transmit Message Configuration Table, a PCI dword operation is required. Tables 6-12 and 6-13 list the address map and the Message Configuration Descriptor layouts. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 135 ...
Page 149
... If PADCNT = 2 and for example, yields the bit pattern 7Eh..FFh..FFh..7Eh There is no indication by MUSYCC if more than PADCNT number of idle codes are inserted. 0 Repeat Message Transmission Disabled. 1 Repeat Message Transmission Enabled. 0 Reserved. ® Mindspeed Technologies Basic Operation 16980h 17180h 17980h 16984h 17184h 17984h group 16180h + (Group_Number[4:7]• ...
Page 150
... Descriptor in shared memory for each active channel. The Buffer Descriptor in each Message Descriptor plus the protocol mode set for the channel dictates the treatment of the incoming bit stream. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 137 ...
Page 151
... BLP and DMAC continue with normal message processing. If the DMAC does not receive more data from shared memory before the BLP must output the next data bit, the BLP outputs another octet of idle code. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 138 ...
Page 152
... BLP detected the end of a message (closing flag or an error condition) in the received data stream. Error conditions include ABT, LNG, ALIGN, BUFF, and ONR errors. Effects: • Interrupt Descriptor in Interrupt Queue with EVENT = EOM, DIR = 0 (if MSKEOM = 0 in Receive Channel Configuration Descriptor). 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 139 ...
Page 153
... Each of these conditions may also generate an interrupt. Effects: • Interrupt Descriptor in Interrupt Queue with EVENT = SINC, DIR = 0 (if MSKSINC = 0 in Receive Channel Configuration Descriptor). • BLP and DMAC continue with normal message processing. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 140 ...
Page 154
... MSKBUFF = 0 in Transmit Channel Configuration Descriptor). • Transmit channel enters abort state where the BLP transmits a repetitive abort sequence of 16 consecutive 1s. • Transmit Buffer Status Descriptor cannot be written. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 141 ...
Page 155
... MUSYCC does not update the transmit Message Descriptor and does not generate an EOB/EOM unless the message is already sent or the buffer is already processed. • MUSYCC stops polling any active transmit channels descriptor. • After the COFA condition subsides, the channel is deactivated. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 142 ...
Page 156
... Degradation of host sub system performance. • Congestion of the PCI bus. Effects: • The Interrupt Descriptor in Interrupt Queue with ERROR = BUFF, DIR = 0 (if MSKBUFF = 0 in Receive Channel Configuration Descriptor). 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 143 ...
Page 157
... The BLP scans for the opening flag of the next HDLC message. • Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared memory. Channel Level Recovery Actions: • None required. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation , the RSYNC input ) 144 ...
Page 158
... The BLP scans for the opening flag of the next HDLC message. • Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared memory. Channel Level Recovery Actions: • None required. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 145 ...
Page 159
... The BLP scans for the opening flag of the next HDLC message. • Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared memory. Channel Level Recovery Actions: • None required. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 146 ...
Page 160
... In the case of an SS7 SUERR, an error is detected in SS7 mode which caused a counter for SS7 related errors to equal or exceed the permitted threshold value. The threshold is stored on a per-channel group basis in the bit field SUET in a Group Configuration Descriptor. Reasons: 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 147 ...
Page 161
... ONR error. Notice there is no mechanism for transparent mode channels to ever enter the IDLE transmission state. 6.4.9.1 Transmit Events Transmit events are informational and require no recovery actions. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 148 ...
Page 162
... That is, ownership of messages was not handed over to MUSYCC in a timely manner. Reason: • Degradation of the host subsystem or application software performance. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 149 ...
Page 163
... In the case of overflow due to host ownership of the buffer, the host has not provided sufficient data buffer space to store received data from the serial interface, and the internal FIFO buffer overflows with received data bits. Reasons: • Degradation of the host subsystem or application software performance. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 150 ...
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... If OOFABT bit field is set the Group Configuration Descriptor, then continue channel activity. That is, received data bits are sampled and eventually copied into shared memory. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation , the RSYNC input ) 151 ...
Page 165
... Repeat Message Transmission section of this document describes the repeat feature fully and is usable for an SS7 application. 6.5.2 Message Filtering Message filtering is always enabled for a receive channel which is configured for SS7-HDLC-CRC16 mode in Table 5-18, Channel Configuration 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Table 5-18, Channel Configuration Descriptor. ® Mindspeed Technologies Basic Operation 152 ...
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... SUERM Octet Counting Octet counting mode is entered if seven consecutive 1s are detected (abort condition), or the received message length exceeds the selected maximum received-frame length register value (long frame error) 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 153 ...
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... BLEN amount of data out the serial port and writes the Transmit Buffer Status Descriptor (and sets OWNER to 0) and moves into the idle state again. 11 step 6 to continue processing the next message. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 154 ...
Page 168
... For self-servicing buffers, the host need not write to any descriptors for receive or transmit operations. MUSYCC writes the Receive Buffer Status Descriptor, which is subsequently used as the Transmit Buffer Descriptor. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Basic Operation 155 ...
Page 169
... JEDEC determines the reflow temperatures based on package thickness. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Specifications Symbol ddi ddo DDC Input, Hi–Z Out Output Lo-Z ® Mindspeed Technologies Value Unit –0.5 to 4.6 V 750 mW 125 °C –55 to +125 °C –0 –0.5 to 3.3 V –0 0 (not to exceed 6 V) –0 0.5 ...
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... I I ddio + ddc I I ddio + ddc I gg Symbol ddio + ddc I I ddio + ddc I gg ® Mindspeed Technologies Value Unit 3.0 to 3.6 V –40 to +85 ° –0.3 to 0.8 V µ 200 to 400 4.75 to 5.25 V 2.3 to 2.7 V Value Unit 2.4 V 0.4 V µ – µ ...
Page 171
... Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Condition — — — — 0 < V < –500 µA out I = 1500 µA out — — — — ® Mindspeed Technologies Min Max Unit 3.0 3 –0.5 0. 0.7V — — ±10 µ ...
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... V dd 0.4V dd 0.3V dd 8478_023 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Min 0 Min high low T cyc ® Mindspeed Technologies Max Unit — ns — ns — V/ns — V Max Unit — ns — ns — V/ns — ptp min dd 159 ...
Page 173
... Signals 8478_025 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Min 1 100 — 50 (3) — — V nom 100 ms (typ rst-clk Three-state ® Mindspeed Technologies Max Unit — ms µ — — V — mV/ns — — Power Fail T fail rst T ...
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... Voltage Test Point test 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Min ( ( — — ( Min ( ( — ( Parameter (1) 0.6 V (1) 0.2 V 0.4 V ® Mindspeed Technologies Max Unit — ns — ns — ns Max Units 14.5 ns — ns — ns — ns Value Unit V ...
Page 175
... Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Parameter (2) 0 and V ). Timing parameters must be met with no more overdrive than this test T val V test Output Current ≤ Leakage Current off Inputs V test Valid V tl ® Mindspeed Technologies Value Unit max test 162 ...
Page 176
... Figure 7-6. PCI Write Multiple Operation PCLK FRAME* CBE[3:0] AD[31:0] PAR IRDY* TRDY* DEVSEL* 8478_029 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Command Byte Enable Address Data 1 Data Command BE BE Address Data 1 Data 2 ® Mindspeed Technologies 163 ...
Page 177
... The EBUS clock waveform characteristics are identical to the PCI clock waveform characteristics (refer to 12 through 7-14 and Figures 7-10 through 7-12). Figure 7-8. ECLK to PCLK Relationship (M66EN = 0) PCLK ECLK 8478_031 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Command BE Address Data 1 V test V test T de ® Mindspeed Technologies Tables 164 ...
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... Input Setup Time to Clock—Point To Point ds 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications T Min — PCI Reset T off EBUS Output EBUS Input Min (1) (1) ® Mindspeed Technologies de Max Units 30 ns Reset Period Three-state Input Ignored Max Units — — ...
Page 179
... Figure 7-11. EBUS Output Timing Waveform PCLK Output Delay 8478_033 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Min Parameter (1) (1) (2) of overdrive (over M66EN = 0 V test M66EN = 1 T val V test ® Mindspeed Technologies Max Units 7 — ns — Value Units V/ns and V ) ...
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... Figure 7-12. EBUS Input Timing Waveform M66EN = 0 PCLK M66EN = 1 Input 8478_034 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications V test test test V tl ® Mindspeed Technologies max 167 ...
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... BLAPSE inserts a variable number of ECLK cycles to extend HOLD deassertion interval until the next bus request. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications are Intel- and Motorola-style write and read transactions Address Data Byte Enables from PCI Data Phase ALAPSE = 0 ELAPSE = 0 ® Mindspeed Technologies BLAPSE = 0 168 ...
Page 182
... BLAPSE inserts a variable number of ECLK cycles to extend BR* deassertion interval until the next bus request. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Address Byte Enables from PCI Data Phase ALAPSE = 0 ELAPSE = 0 ® Mindspeed Technologies Data BLAPSE = 0 169 ...
Page 183
... Low Threshold Voltage TL V Hysteresis H 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Tables 7-15 Parameter 1 Parameter Parameter 0.7* VDDi ® Mindspeed Technologies through 7-18 and Figures 7-15 Min Max Units DC 8.192 ±10% MHz — — Min Max Units ...
Page 184
... Edge) 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications Parameter (1) (1) (2) of overdrive (over test test val test test ® Mindspeed Technologies Value Units V/ns and V ). Timing parameters must be met with test val test max ...
Page 185
... Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications V V test test T val test val test V tl Airflow–LFM (LMS) 0 (0.000) 50 (0.256) 100 (0.505 θ × Table 7-1). 7-19). 7-2). 7-1). ® Mindspeed Technologies max test V V max test 200 (1.01) 400 (2.03 172 ...
Page 186
... Figure 7-19. 208-Pin Metric Quad Flatpack (MQFP) TOP VIEW D D3 PIN # 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications 208 MQFP 1.30 REF. ® Mindspeed Technologies BOTTOM VIEW ALL DIMENSIONS IN MILLIMETERS MIN. NOM. MAX 3.70 ---- 4. 0.25 0.33 ---- ...
Page 187
... Preliminary Information / Mindspeed Proprietary and Confidential Electrical and Mechanical Specifications 17.00 + 0.70 15.00 – 0.50 A1 BALL PAD CORNER 1.00 REF 0. PLACES ® Mindspeed Technologies 30˚ TYP + 0.10 0.50 – 0.10 SEATING PLANE 0.80 ± 0.05 1.76 ± 0.21 0.40 ± 0.10 0.56 ± 0.06 8478_048 174 ...
Page 188
... Table 8-1. Number Representation Type Binary Decimal Octal Hexadecimal 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Conventions Table 8-1. The suffix can be dropped for clarity when the context Suffix ® Mindspeed Technologies Example 01b, 1010b 01d, 999d 01o, 174o 01h, 08E002FCh 175 ...
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... Preliminary Information / Mindspeed Proprietary and Confidential 0 (MSB Bit Stream = 10101111...... Bit Stream = 11110101...... 3 MSB 2 Bits 7 <- 0 Byte Stream = Byte 0, Byte 1, Byte 2, Byte 3...... 10h ® Mindspeed Technologies Terms, Definitions, and Conventions (LSB Table 8-3 illustrates this (LSB Table 8- LSB Bits 7 <- 0 Data 32h ...
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... FREC Frame Recovery HDLC High-Level Data Link Control IC Idle Code INTC Interrupt Controller IRAM Internal RAM ISDN Integrated Service Digital Network 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Terms, Definitions, and Conventions 76h ® Mindspeed Technologies Data 54h 32h 10h 177 ...
Page 191
... SUERM Octet Count Increment SS7 Signaling System 7 SUERM Signal Unit Error Rate Monitor SUERR Signal Unit Error Rate Interrupt SUET Signal Unit Error Threshold TS Time Slot TX (Tx) Transmit/Transmitter 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Terms, Definitions, and Conventions ® Mindspeed Technologies 178 ...
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... An 8-bit portion of a channelized frame which repeats every 125 µs and represents a time slot 64 kbps signal. In channelized T1 and E1 frames, 24 and 32 time slots operate at 64 kbps. word A field made binary bits or 2 bytes concatenated. 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Terms, Definitions, and Conventions ® Mindspeed Technologies 179 ...
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... Table A-1. IEEE Std. 1149.1 Instructions Bit 2 Bit 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Bit 0 Instruction 0 EXTEST 1 SAMPLE/PRELOAD 0 Private 1 Private 0 Private 1 Private 0 Private 1 BYPASS ® Mindspeed Technologies Register Accessed Boundary Scan Boundary Scan — — — — — Bypass 180 ...
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... TRST~ TMS TDI t pwh TCK TDO 8478_043 28478-DSH-002-E Preliminary Information / Mindspeed Proprietary and Confidential Description pwl per ® Mindspeed Technologies JTAG Interface Min Max Unit — 100 ns 0 per per 0 per per 100 — — — ns — — ...
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... Newport Beach, CA 92660 © 2006 Mindspeed Technologies ® , Inc. All rights reserved. Information in this document is provided in connection with Mindspeed Technologies ® ("Mindspeed ® ") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever ...