28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 75

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Figure 4-4.
28478-DSH-002-E
GENERAL NOTE:
1. Nx64 Mode employs N time slots with 8 bits (0–7) per time slot.
2. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
3. Assertion of TSYNC must precede transmission of bit 0 of a frame by exactly 4 line clock periods due to the internal buffer scheme used for
4. RSYNC and TSYNC signals must be provided for every received and transmitted frame in Nx64 mode.
5. If N = 1, the minimum, then 8 bits/frame = 64 kHz. If N = 128, the maximum, then 1024 bits/frame = 8.192 MHz.
6. Relationships between the various configurations of active edges for the synchronization signal and the data signal are shown using a
7. All received signals (e.g., RSYNC, RDAT, TSYNC) are sampled on the specified clock edge (e.g., RCLK, TCLK). All transmit data signals
8. In configuration (a), synchronization and data signals are sampled or latched on a rising clock edge.
9. In configuration (b), synchronization signal is sampled on a rising clock edge, and the data signal is sampled or latched on a falling clock
10. In configuration (c), synchronization signal is sampled on a falling clock edge, and the data signal is sampled or latched on a rising clock
11. In configuration (d), synchronization and data signals are sampled or latched on a falling clock edge.
transmitting of Nx64 mode data bits.
common clock signal for receive and transmit operations. Note the relationship between the frame bit (within RDAT, TDAT) and the frame
synchronization signal (e.g., RSYNC, TSYNC).
(TDAT) are latched on the specified clock edge.
edge.
edge.
8478_016
RSYNC-FALL(d)
RSYNC-RISE(a)
RSYNC-RISE(b)
RSYNC-FALL(c)
RDATA-RISE(a)
TSYNC-RISE(a)
TSYNC-RISE(b)
TSYNC-FALL(c)
TSYNC-FALL(d)
RDATA-RISE(c)
TDATA-FALL(b)
TDATA-FALL(d)
RDAT-FALL(b)
RDAT-FALL(d)
Transmit and Receive Nx64 Mode
TDAT-RISE(a)
TDAT-RISE(c)
RCLK
TCLK
Preliminary Information / Mindspeed Proprietary and Confidential
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