28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 126

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

6.1.4
The typical power-up or reset initialization sequence is as follows:
1. PCI configuration.
2. Soft Chip Reset.
3. Allocate Shared Memory.
4. Initialize Shared Memory Channel Group Descriptors and time slot map.
5. Write the Group Base Pointer values.
6. Allocate interrupt queue and initialize it.
7. Set Message Descriptor pointers.
8. Perform Global Initialization, waiting for SACK.
9. Perform Group Initialization, waiting for SACK between each service request.
6.2
A sequence of hierarchical initializations must occur after resets. The levels of hierarchy are as follows:
1. PCI Configuration—only after hardware reset
2. Global Configuration
3. Interrupt Queue Configuration
4. Channel Group(s) Configuration
6.2.1
After power-up or a PCI reset sequence, MUSYCC enters a holding pattern, waiting for PCI configuration cycles
directed specifically for MUSYCC at the PCI bus and PCI slot MUSYCC resides in.
PCI configuration involves PCI read and write cycles initiated by the host and performed by a host-bus-to-PCI-bus
bridge device. The cycles are executed at the hardware signal level by the bridge device. The bridge device polls all
possible slots on the bus it controls for a PCI device and then iteratively reads the configuration space for all
supported functions on each device. All information from the basic configuration sequence is forwarded to the
system controller or host processor controlling the bridge device.
During PCI configuration, the host can perform the following configuration for MUSYCC’s Function 0, HDLC
Network Controller function:
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28478-DSH-002-E
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Read PCI configuration space (Device Identification, Vendor Identification, Class Code, and Revision
Identification).
Allocate 1 MB system memory range and assign the Base Address register using this memory range.
Allow fast back-to-back transactions.
Group Initialization - Receive Group 0–8
Group Initialization - Transmit Group 0–8
NOTE:
Recommended Initialization Sequence
Configuration
PCI Configuration
Preliminary Information / Mindspeed Proprietary and Confidential
SACK for Global Initialization is not written until the Global and Interrupt Queue Descriptors
are read from memory.
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®
Basic Operation
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