28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 100

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28478G-18

Manufacturer Part Number
28478G-18
Description
Multichannel Synchronous Communications Controller 208-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of 28478G-18

Package
208BGA
Maximum Data Rate
32768 Kbps
Transmission Media Type
Wire
Power Supply Type
Analog
Typical Supply Current
250 mA
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
Maximum Operating Supply Voltage
3.6 V
Table 5-13.
5.2.2.7
The time slot map consists of 32 time slot descriptors. One descriptor maps four time slots. The entire map
contains configuration information for 128 time slots. The serial port does not need to support 128 time slots all the
time. Any number of time slots from 1 to 128 is supportable.
The time slot map is used when the serial port associated with a channel group is configured in one of the
channelized modes: T1, E1, 2xE1, 4xE1, or Nx64. MUSYCC supports mapping of up to 128 time slots from a
channelized bit stream with up to 32 logical channels in each channel group.
Numerous mappings of time slots to channels are possible. Multiple time slots can be mapped to a single channel;
however, each time slot can map to only one channel at a time. When the number of active time slots exceeds the
number of channels in a group (greater than 32 time slots), and each time slot requires a separate channel,
MUSYCC can be configured to internally connect 2 or 4 channel groups together to provide up to 64- or 128-
channel support, respectively.
Two time slot maps are required for each channel group, one for transmit functions and one for receive functions.
The two maps are configured independently. Each map consists of 128 successive 8-bit fields, each corresponding
to one time slot. The bit field includes the following information:
For disabled time slots, modes and logical channels can be assigned, but the information does not apply to the
operation of the channel.
For enabled time slots, the valid modes of operation include the following:
The logical channel number represents the channel in the channel group handling the bit stream from the time slot
or slots assigned to it. The value of the channel number ranges from 0–31.
28478-DSH-002-E
Field
31:28
27:16
15:12
11:0
Time Slot Enabled/Time Slot (TSEN) Mode of Operation (64 kbps, 56 kbps, subchannel) indicator
Logical channel number (0–31) associated with time slot (CH)
64 kbps Mode: all 8 bits of time slot are assigned to one channel.
56 kbps Mode: first 7 bits of time slot are assigned to one channel. Last bit, Most Significant Bit (MSB), is
unassigned and considered disabled.
Subchannel Mode, Bit 0 Disabled: first bit, Least Significant Bit (LSB), of time slot is unassigned. Each of the
next 7 bits in time slot can be individually enabled and independently mapped to any channel in a channel
group.
Subchannel Mode, Bit 0 Enabled: first bit (LSB) of time slot is always enabled and assigned to a channel in a
channel group. Each of the next 7 bits in time slot can be individually enabled and independently mapped to
any channel in a channel group.
Bit
MAXFRM2[11:0]
MAXFRM1[11:0]
Message Length Descriptor
Name
RSVD
RSVD
Time Slot Map
Preliminary Information / Mindspeed Proprietary and Confidential
Value
0
0
Mindspeed Technologies
Reserved.
Defines a limit for the maximum number of octets allowed in a received HDLC message.
Valid values for the register range from 1 to 4094 depending on FCS16 or FCS32.
Reserved.
Defines a limit for the maximum number of octets allowed in a received HDLC message.
Valid values for the register range from 1 to 4094 depending on FCS16 or FCS32.
®
Description
Memory Organization
87

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