28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 43

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

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All other PCI cycles are ignored by MUSYCC. Only memory cycles are mapped to operations on the EBUS.
As a PCI-master, MUSYCC generates the following PCI bus operations:
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•
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2.1.3
This section describes how MUSYCC implements the required PCI configuration register space to provide
configuration registers. These registers satisfy the needs of current and anticipated system configuration
mechanisms, without specifying those mechanisms or otherwise placing constraints on their use. The configuration
registers provide the following functions:
•
•
•
MUSYCC responds only to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request on to
another PCI bus, are ignored.
MUSYCC is a two-function PCI agent; therefore, it must implement configuration space for both functions.
The PCI controller in MUSYCC responds to configuration and memory cycles, but only memory cycles cause bus
activity on the EBUS.
The address phase during a MUSYCC configuration cycle indicates the function number and register number
being addressed which can be decoded by observing the status of the address lines AD[31:0].
the address lines during the configuration cycle.
Figure 2-2.
The value of the signal lines AD[10:8] selects the function being addressed. MUSYCC supports Functions 0 and 1
and will not respond if another function is selected.
28478-DSH-002-E
FOOTNOTE:
(1)
(2)
(3)
MUSYCC supports Functions 0 and 1.
MUSYCC supports Registers 0 through 15, inclusive.
MUSYCC supports Type 0 configuration cycles.
Memory Write and Invalidate (treated like Memory Write)
Memory Read Multiple (generated only in master mode)
Memory Write
Dual Address Cycle
Full device relocation, including interrupt binding
Installation, configurations, and booting without user intervention
System address map construction by device-independent software
Address Lines During Configuration Cycle
PCI Configuration Space
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Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
Don't
Care
11 10
Function
Number
3-Bit
8 7
(1)
®
Register
Number
6-Bit
(2)
2 1
Number
Type
2-Bit
0
Bit
Number
(3)
Figure 2-2
Host Interface
shows
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