28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 86

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 5-1.
The first four registers in each group (shown in bold-type in
These registers are accessed by the host using direct reads and writes to the corresponding register map address.
The remaining registers have corresponding locations within shared memory, and the host accesses the shared
memory image rather than the internal registers. Regardless, the values within MUSYCC are always the values
used during device operation. After configuring the shared memory image of these registers, the host issues a
service request by writing directly into the Service Request Descriptor. This causes MUSYCC to copy the image
from shared memory.
Each supported channel group requires its own group structure to operate. The Dual Address Cycle Base Pointer,
Interrupt Status Descriptor, Global Configuration Descriptor, and the Interrupt Queue Descriptor are common
among all supported groups.
The Transmit Time Slot Map and the Transmit Subchannel Map are write-only areas within MUSYCC; reading from
these areas results in all 1s being returned.
The Service Request Descriptors are locations within MUSYCC where commands can be directed to individual
channel groups. The host writes a service request (a command) directly into the corresponding group’s register.
MUSYCC behaves as a PCI slave as this write is performed. The action resulting from the command may cause
MUSYCC to read or write locations from shared memory. While MUSYCC accesses shared memory, it behaves as
a PCI master and arbitrates for control of the bus autonomously.
MUSYCC’s registers can be initialized before or after shared memory resident descriptors are initialized. The
recommended sequence is to configure shared memory descriptors first, then copy the relevant information to
MUSYCC’s registers via the service request mechanism.
The first four sets of pointers for each channel group, listed in
memory. MUSYCC does not keep these values internally although they are accessed regularly during channel
processing. The remaining locations have a corresponding register within MUSYCC.
28478-DSH-002-E
Receive BIST Status
Transmit BIST Status
FOOTNOTE:
(1)
(2)
(3)
MUSYCC automatically maps Group 1 through 7 addresses for these registers to the Group 0 address (shown). For example, accessing
address 00E00h in MUSYCC (address for Group 1 Global Configuration register) automatically maps to address 00600h and the contents
of 00600h is read or written.
The following descriptors are mapped to Internal RAM: Transmit Time Slot Map, Transmit Subchannel Map, Transmit Channel
Configuration Table, Receive Time Slot Map, Receive Subchannel Map, and Receive Configuration Table. Host must not access internal
RAM while channels are active. Updates to RAM must be performed via a service request.
The receive/transmit BIST diagnostic status registers.
Register Map
MUSYCC Register Map (2 of 2)
(3)
(3)
NOTE:
Preliminary Information / Mindspeed Proprietary and Confidential
Upon channel activation, shared memory and internal registers must be initialized, valid,
and available to MUSYCC. MUSYCC uses the information within the shared memory
descriptors to transfer data between the serial interface and shared memory. MUSYCC
assumes the information is valid once a channel is activated.
Mindspeed Technologies
0
1
(Byte Offset from Base Address Register)
2
Table
Table
5-1) are located exclusively within MUSYCC.
®
5-2, are pointer locations exclusive to shared
3
00640h
00644h
Group
4
Memory Organization
5
6
7
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