28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 56

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

If a parity error occurs, the master that generated the cycle (whether it asserted PERR* or detected it) reports
parity errors to the host. MUSYCC does this by generating an Interrupt Descriptor. It also sets the Data Parity
Detected bit (for masters only) in the Status register in the appropriate function’s PCI configuration space and sets
the Detected Parity Error (for masters or targets) in the same register if MUSYCC is the agent that detected the
error.
PERR* reports errors on the data phases. MUSYCC not only asserts PERR* when appropriate, but monitors
PERR* for its own memory transactions and notifies the host of the parity error.
SERR* reports parity errors on the address phases. It is assumed that this open drain PCI signal is tied directly to
the host’s system error pin. MUSYCC does not generate an Interrupt Descriptor if it detects a parity error on an
address phase, nor does it respond to SERR* assertion.
2.2.6
In PCI systems, achieving high bus throughput works against achieving low bus latency. As devices burst more
data, they keep the bus longer, causing other devices waiting for the bus to experience a longer acquisition latency
as a result.
A PCI bus master introduces latency each time it uses the PCI bus to perform a transaction. The bus master
latency is a function of the following:
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When MUSYCC requests the PCI bus, it needs the bus to transfer data between an internal FIFO buffer and
shared memory across the PCI bus with either a read or a write access. While MUSYCC waits for the bus to be
granted, and then while MUSYCC transfers the data, another equal-sized internal FIFO buffer is simultaneously
being filled or emptied at the serial interface. When MUSYCC requests the bus, it has data to transfer, and also has
a finite amount of time (which is directly related to the speed of the serial line clock) before a separate FIFO buffer
at the serial interface overflows or underflows.
For an application with many logical channels, MUSYCC requires a new access cycle on the PCI bus more
frequently than an application with fewer logical channels. If FIFO buffer space is evenly distributed across all
channels, more channels result in less FIFO buffer space per channel, and FIFO buffer space must be cleared
more frequently.
Conversely, an application with high data rate serial interfaces requires a new access cycle on the PCI bus more
frequently than an application with a low data rate serial interface, because the FIFO buffer fills faster in the former.
Acquiring the PCI bus requires having to deal with arbitration latency, which is defined as the number of PCI clock
cycles a master must wait after asserting its REQ* and before asserting the GNT* signal. This number is a function
of the system’s arbitration algorithm and takes into account the sequence in which masters are given access to the
bus and the latency timer of each master. Arbitration latency is also affected by the loading of the system and how
efficiently the bus is being utilized.
28478-DSH-002-E
Behavior of the master
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Behavior of the target
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State of the GNT* signal
Bus command used (read, write,...)
Burst length
Master data latency for each data phase
Value of Latency Timer
Bus command used (read, write,...)
Target latency
PCI Throughput and Latency Considerations
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Host Interface
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