28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 62

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

MUSYCC performs a PCI target disconnect after the first data phase of any burst read cycle to either Function 0 or
Function 1. Therefore, the PCI bridge must be able to fragment a burst access into a single phase read or 1–
4 phase burst writes as controlled by the target disconnect.
Assuming the EBUS is connected to byte-wide peripheral devices, the EBUS interface uses the lower 20 bits from
PCI address lines AD[19:0] to construct a byte address for the EBUS. Specifically, PCI address lines AD[19:2] are
converted to EBUS address lines EAD[17:0] by shifting out the two least significant bits, AD[1:0]. This allows for
byte-level addressing for up to 4 byte-wide devices on the EBUS. Given the above, the EBUS provides an 18-bit
addressing structure allowing byte addressing of up to four banks of 256 kB address space each.
The EBUS interface transfers 32 bits of the data lines between the EBUS and the PCI bus. The byte-enable signal
lines EBE[3:0]* are transferred from the PCI byte-enable signal lines CBE[3:0]* to the EBUS, and indicate which
byte(s) in the data dword are valid.
Figure 3-3.
3.1.3
The ECLK is derived from the PCI clock and runs at up to a 33 MHz clock rate. This operation is controlled by the
M66EN input on Revision C and later devices. An asserted M66EN input implies that the overall system is
operating at a 66 MHz PCI clock rate; the ECLK is running at half of the PCI clock rate. Otherwise, the ELCK is
operating at the same rate as the PCI clock frequency. In order to ensure that the ELCK is properly operational, the
M66EN input state shall not be changed during the whole operational period.
The EBUS clock output can be disabled by setting the ECKEN bit field (see
ECLK output is three-stated.
28478-DSH-002-E
GENERAL NOTE:
1. Byte Enable 0–EBE[0]* signals if EAD[7:0] are valid data bits during data phase.
2. Byte Enable 1–EBE[1]* signals if EAD[15:8] are valid data bits during data phase.
3. Byte Enable 2–EBE[2]* signals if EAD[23:16] are valid data bits during data phase.
4. Byte Enable 3–EBE[3]* signals if EAD[31:24] are valid data bits during data phase.
5. An active low signal is denoted by a trailing asterisk (*).
EBUS Address/Data Line Structure
Clock
8478_009
Preliminary Information / Mindspeed Proprietary and Confidential
Address Lines–EAD[31:0] During Address Phase
Data Lines–EAD[31:0] During Data Phase
All 32 bits transferred between PCI bus and EBUS.
The byte enable lines indicate which bits are valid in
the 32-bit dword during the data phase.
31
31
00000000000000
YYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYY
always 0 during
address phase
Upper 12 Bits
Figure 3-3
Mindspeed Technologies
illustrates both data and data configurations of the 32-bit word.
20 19 17
00
Byte addressing with bits 19 and 18
AD[19:2] transferred from PCI Bus
YYYYYYYYYYYYYYYYYY
always 0 during address phase.
to EAD[17:0] on the EBUS.
Lower 20 Bits
®
Table
5-6). In the disabled state, the
0 Bit Number
0 Bit Number
Expansion Bus (EBUS)
49