28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 109

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

•
The OWNER bit is a generic term for any descriptor. In a Transmit Buffer Descriptor it is called MUSYCC; in a
Receive Buffer Descriptor it is called host. The names are different to indicate that the active sense of the owner bit
is different between transmit and receive functions.
In addition to the above list of fields, Transmit Buffer Descriptors also include the following fields:
•
•
•
•
•
IC, PADEN, PADCNT, and REPEAT are valid only when EOM = 1.
Tables 5-22
Table 5-22.
28478-DSH-002-E
Field
26:25
23:16
Buffer Length (BLEN)
End of Message Indicator (EOM)
Idle Code Selection (IC)
Pad Enable (PADEN)
Pad Count (PADCNT)
Repeat Packet Enable (REPEAT)
Bit
31
30
29
28
27
24
and
Transmit Buffer Descriptor (1 of 2)
PADCNT[7:0]
5-23
OWNER
IC[1:0]
PADEN
Name
EOM
EOBI
NP
—
list the transmit and receive buffer descriptors and definitions.
Preliminary Information / Mindspeed Proprietary and Confidential
Value
—
0
1
0
1
0
1
0
1
0
0
1
2
3
0
1
Mindspeed Technologies
HOST Owns Buffer. HDLC channel remains in idle mode while polling this bit periodically (if
NP = 0) until host relinquishes control to MUSYCC by setting OWNER = 1. In transparent mode
the channel is deactivated.
MUSYCC Owns Buffer. Continue processing data buffer normally.
Poll Enabled. If OWNER = 0, host-owned, MUSYCC polls the message descriptor periodically
while in idle mode until OWNER = 1.
Poll Disabled. If OWNER = 0, then waits for a Channel Activate or Jump Service Request from
host.
Data Buffer w/o End of Message.
Data Buffer w/ End of Message.
End of Buffer Interrupt Disabled. When no more data can be taken from or put into a data buffer,
an EOB interrupt is not generated.
End of Buffer Interrupt Enabled.
Reserved.
Idle Code Select – 7Eh
Idle Code Select – FFh
Idle Code Select – 00h
Reserved.
Pad Fill Disabled. One shared opening/closing flag (7Eh) is inserted before sending next
message.
Pad Fill Enabled. Also, see PADCNT bit field.
Pad Count. When PADEN = 1, PADCNT indicates the minimum number of idle codes to be
inserted between the closing flags and the next opening flag (7Eh). If PADCNT = 2 and IC = 1, for
example, MUSYCC outputs the bit pattern 7Eh..FFh..FFh..7Eh. There is no indication by MUSYCC
if more than PADCNT number of idle codes are inserted.
®
Description
Memory Organization
96