28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 161

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

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Effects:
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Channel Level Recovery Actions:
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6.4.9
MUSYCC supports a transparent mode where no distinction is made between information and non-information bits
in the data bit stream. This mode is assigned on a per channel and direction basis by the bit field PROTOCOL in
the Channel Configuration Descriptor.
In transparent mode, the following characteristics apply:
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Unlike HDLC mode, MUSYCC does not poll a host-owned Transmit Buffer Descriptor during transparent mode.
When the internal buffer is empty and no more transmit data is available from shared memory (i.e., host-owned
buffer), MUSYCC does the following:
1. Issues an ONR error.
2. Enters the channel deactivate state, sending idle code on the affected channel.
If the host wants to send any more data on that channel, the host must reactivate any transparent mode transmit
channel that has issued an ONR error.
Notice there is no mechanism for transparent mode channels to ever enter the IDLE transmission state.
6.4.9.1
Transmit events are informational and require no recovery actions.
28478-DSH-002-E
A Short SS7 message increments the SS7 counter.
An FCS error in the SS7 message increments the SS7 counter.
An Octet alignment error in the SS7 message.
Accumulation of 16 “octet count” type errors increments counter.
The Interrupt Descriptor in Interrupt Queue with ERROR = SUERR, DIR = 0 (if MSKSUERR = 0 in Receive
Channel Configuration Descriptor).
The BLP scans for the opening flag of the next HDLC message.
Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared
memory.
None required.
All data bits are transferred between shared memory and the serial interface without protocol support such as
those listed for the HDLC mode.
Host must maintain the necessary data transfer rates at all times by providing Message Descriptors and data
buffers for both the transmit and receive channels.
The host must always set the bit field EOM to 0 in each Transmit Buffer Descriptor. Setting EOM to 1 causes
indeterminate results. Due to EOM = 0, the other Transmit Buffer Descriptor bit fields—IC, PADEN, PADCNT,
and REPEAT—are ineffective.
NOTE:
Transparent Mode
Transmit Events
Preliminary Information / Mindspeed Proprietary and Confidential
Receiving 256 unerrored SS7 messages decrements the SS7counter.
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Basic Operation
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