28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 48

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Register 2, Address 08h
This location contains the Class Code and Revision ID registers. The Class Code register contains the Base Class
Code, Sub-Class Code, and Register Level Programming Interface fields, used to specify the generic function of
MUSYCC. The Revision ID register denotes the version of the device.
Table 2-5.
Register 3, Address 0Ch
Table 2-6.
28478-DSH-002-E
FOOTNOTE:
(1)
FOOTNOTE:
Field
Field
31:24
23:16
29:27
23:16
15:11
15:8
10:8
Bit
7:0
Bit
7:0
Registers shared between Function 0 and 1.
31
30
26
25
24
Class Code
Revision ID
Built-In Self Test (BIST)
Capable
Start BIST
Reserved
BIST Error in the Interrupt
Queue
BIST Error in the Transmitter
BIST Error in the Receiver
Header Type
Latency Timer
Reserved
An active-low signal is denoted by a trailing asterisk (*).
Register 2, Address 08h
Register 3, Address 0Ch
(1)
Name
Name
Preliminary Information / Mindspeed Proprietary and Confidential
Reset
Value
Reset
Value
Mindspeed Technologies
02h
80h
01h
80h
—
—
—
0
1
0
0
0
0
0
Type
RO
RO
RO
RO
Type
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Base Class Code: Network Controller.
Sub-Class Code: Other Network Controller.
Register Level Programming Interface: Indicates there is nothing special about
programming MUSYCC.
Denotes the revision number of MUSYCC. Rev A = 0Ah, Rev B = 0Bh,
Rev C = 0Ch, etc.
Returns 1 if device supports BIST. Returns 0 if it does not support BIST.
Writes 1 to invoke BIST. Device resets the bit when BIST is complete.
Software should fail the device if BIST is not complete after two seconds.
Unused.
After “Start BIST” bit gets reset, this bit indicates if there were any errors in
the interrupt queue RAM areas.
After “Start BIST” bit gets reset, this bit indicates if there were any errors in
the transmit queue RAM areas.
After “Start BIST” bit gets reset, this bit indicates if there were any errors in
the receive queue RAM areas.
MUSYCC is a multifunction device with the standard layout of configuration
register space.
The latency timer is an 8-bit value that specifies the maximum number of PCI
clock cycles that MUSYCC can keep the bus after starting the access cycle by
asserting its FRAME*. The latency timer ensures that MUSYCC has a
minimum time slot for it to own the bus, but places an upper limit on how
long it will own the bus.
Unused.
®
Description
Description
Host Interface
35