28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 147

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

For all HDLC modes which require FCS calculations, the polynomials used to calculate the FCS are according to
ITU-T Q.921 and ISO 3309-1984.
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6.4.2
For HDLC modes only, MUSYCC supports the use of opening and closing message flags. The 7Eh (01111110b)
flag is the opening and closing flag. An HDLC message is always bounded by this flag at the beginning and the end
of the message.
MUSYCC supports receiving a shared flag where the closing flag of one message can act as the opening of the
next message. MUSYCC also supports receiving a shared 0 bit between two flags, i.e., the last 0 bit of one flag is
used as the first 0 bit of the next flag.
MUSYCC can be configured to transmit a shared flag between successive messages by configuring the bit field
PADEN in each Transmit Buffer Descriptor. MUSYCC does not transmit shared 0 bits between successive flags.
6.4.3
Seven consecutive 1s constitute an abort flag. Receiving the abort code causes the current frame processing to be
aborted and terminates further data transfer into shared memory. After detecting the abort code, MUSYCC enters
a mode searching for a new opening flag.
Notification of this detected condition is provided by the receive Buffer Status Descriptor or an Interrupt Descriptor,
indicating the error condition Abort Flag Termination.
In cases where received idle codes transition to an abort code, an Interrupt Descriptor is generated toward the host
indicating the informational event Change to Abort Code. All received abort codes are discarded.
6.4.4
MUSYCC provides 0-bit insertion and deletion when it encounters five consecutive 1s within a frame. In the
receiver, a 0 bit is de-inserted, and in the transmitter a 0 bit is inserted after five 1s are seen.
6.4.5
A group of bits specified in a Transmit Buffer Descriptor specifies the data to be transmitted at the transmit channel
after the end of a current message has been transmitted. The bits are collectively known as the Message
Configuration Descriptor and include the specifications for the following:
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28478-DSH-002-E
CRC-16:
CRC-32:
Idle Code specification, IC
Inter-message Pad Fill Enable, PADEN
Inter-message Pad Fill Count, PADCNT
Repeat Message Transmission, REPEAT
Opening/Closing Flags
Abort Codes
Zero-Bit Insertion/Deletion
Message Configuration Bits
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Basic Operation
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