28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 145

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

streaming process may or may not have a particular alignment with respect to that channel's assigned time slot
boundaries, depending upon whether the channel is configured to operate in HDLC or Transparent mode.
For HDLC mode channels, data stream processing begins immediately upon channel activation. Any type of
alignment of a HDLC channel's data stream with respect to its assigned serial port time slots is unnecessary, and
MUSYCC disables time slot synchronization for that channel. Therefore, no specific alignment exists or needs to
exist between the first bit of a HDLC message and the first bit of the assigned channel time slot.
After activation of a Transparent mode channel, the SFALIGN setting selects whether that channel's bit-level
processor either waits for a frame synchronization signal from the internal flywheel, or an external synchronization
signal from the serial port sync input pin before starting the data stream process. The selected synchronization
signal (internal or external) thus determines the alignment of that channel's data stream with respect to its
assigned serial port time slot. This time slot alignment mechanism ensures Transparent mode channel's are able to
transfer sampled voice data streams to and from bytes stored in Shared Memory while maintaining the alignment
of those bytes with respect to the serial port time slot. In Transparent mode MUSYCC is required to point to a
MUSYCC-owned buffer prior to a channel activation service request.
For Transparent mode hyperchannels, where multiple time slots are mapped to a single channel, the first byte of
data to and from the Shared Memory buffer is aligned to the lowest numbered serial port time slot mapped to that
hyperchannel. If the lowest numbered time slot mapped to that hyperchannel equals time slot 12, the bit-level
processor aligns the first byte of Shared Memory buffer data to time slot 12 and the next byte of data to the next
higher numbered time slot that is also mapped to that hyperchannel. This sequence of time slot mapped alignment
is true for all Transparent mode hyperchannel cases except when time slot 0 is the lowest numbered time slot
mapped. In which case, the first byte of Shared Memory buffer data is transferred to the next higher numbered time
slot. For example, a Transparent mode hyperchannel mapped to time slot 0, and time slot 1 would output the first
byte of Shared Memory data during time slot 1 and would write receive data from time slot 1 into the first byte of the
Shared Memory buffer.
6.3.20
Upon channel activation and any necessary frame alignment, MUSYCC must fetch Message Descriptors from
shared memory to start the flow of message bits into and out of shared memory.
As a Buffer Descriptor is fetched, MUSYCC checks the owner-bit to verify if the buffer is serviceable by MUSYCC.
If the owner bit indicates that the host still owns the buffer, the host has not yet prepared the data in the buffer for
processing. This may or may not be an error condition. In this case, MUSYCC also must check the no-poll bit in the
same descriptors to determine if polling for MUSYCC ownership is enabled.
If the host owns the buffer and polling is disabled, the channel direction is suspended from processing messages
until the host intervenes with a subsequent channel activation or channel jump request. The channel is not capable
of leaving this suspended state autonomously.
If the host owns the buffer and polling is enabled, the channel direction is suspended from processing messages
and MUSYCC periodically polls the owner bit in the Buffer Descriptor to verify that the buffer is ready for MUSYCC.
The channel is capable of leaving this suspended state autonomously.
The frequency of polling is controlled independently for each channel group by the SFALIGN (superframe
alignment) and POLLTH (poll throttle) bit fields in the Group Configuration Descriptor.
The SFALIGN bit field defines the source of the synchronization event to be used by MUSYCC. The source is either
an internal flywheel method or an external signal at the serial port.
28478-DSH-002-E
NOTE:
Descriptor Polling
Preliminary Information / Mindspeed Proprietary and Confidential
Time slot counter or flywheel time base method uses a 7-bit counter. As each bit is
serviced, over 32 channels with 8 bits per channel in a 2.048 MHz data stream, the counter
is incremented. When the counter rolls over to 0, a Beginning of Frame is declared. At
2.048 MHz, 256 bits represents 125 ms.
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Basic Operation
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