28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 113

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 5-27.
5.2.4.10
The bit fields Inhibit Buffer Status Descriptor (INHTBSD for transmitters or INHRBSD for receivers) in the Group
Configuration Descriptor specify whether or not MUSYCC writes a Buffer Status Descriptor to shared memory after
the end of the current message has been detected.
If INHTBSD/INHRBSD is set to 0, MUSYCC:
1. Assumes the Message Pointer points to the current Message Descriptor.
2. Overwrites the Buffer Descriptor field with the Buffer Status Descriptor field.
3. Fetches the next Message Pointer from the descriptor.
4. Reads the next Message Descriptor.
5. Writes the pointer to the new descriptor into the Message Pointer in shared memory.
If INHTBSD/INHRBSD is set to 1, MUSYCC:
1. Assumes the Message Pointer points to the next Message Descriptor.
2. Reads the next Message Descriptor.
3. Writes the Next Message Pointer from the descriptor into the Message Pointer in shared memory.
5.2.5
MUSYCC generates interrupts for a variety of reasons. Interrupts are events or errors detected by MUSYCC during
bit-level processing of incoming serial data streams. Interrupts are generated by MUSYCC and forwarded to the
host for servicing. Individual types of interrupts can be masked from being generated by setting the appropriate
interrupt mask or interrupt disable bit fields in various descriptors. The interrupt mechanism, each individual
interrupt, and interrupt controlling mechanisms are discussed in this section.
5.2.5.1
MUSYCC employs a single Interrupt Queue Descriptor to communicate interrupt information to the host. This
descriptor is stored in MUSYCC in an internal register. The descriptor in this register space stores the location and
size of an interrupt queue in shared memory. MUSYCC requires this information to transfer interrupt descriptors it
generates to shared memory for the host to use. MUSYCC writes Interrupt Descriptors directly into the shared
memory queue using PCI bus master mode. MUSYCC’s PCI interface must be configured to allow bus mastering.
The Interrupt Queue Descriptor is initialized by the host issuing a service request to MUSYCC to read of a copy of
the Interrupt Queue Descriptor from shared memory. Another method of initialization is for the host to directly write
the information into the appropriate register space within MUSYCC.
Tables 5-28
28478-DSH-002-E
Field
31:0
Bit
through
DATAPTR[31:0]
Data Buffer Pointer
Name
Message Descriptor Handling
Interrupt Level Descriptors
Interrupt Queue Descriptor
5-30
list the details of the Interrupt Queue Descriptor.
Preliminary Information / Mindspeed Proprietary and Confidential
Value
—
Mindspeed Technologies
The 32-bit address in this descriptor serves as a byte pointer to the first octet of a data buffer.
®
Description
Memory Organization
100