28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 35

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 1-4.
28478-DSH-002-E
190
144-146,
149-152,
154-155,
158-163,
166-170,
173-174,
176-180,
183-184,
187-189
199, 200,
203, 204
192
193
194
195
196
197
198
Pin No.
MQFP
CN8478 Hardware Signal Definitions (1 of 6)
WR* (R/WR*)
EINT*
HOLD
BGACK*
ECLK
EAD[31:0]
EBE[3:0]*
RD*
(DS*)
ALE*
(AS*)
(BR*)
HLDA
(BG*)
Pin Label
Preliminary Information / Mindspeed Proprietary and Confidential
Expansion Bus Clock
Expansion Bus
Address and Data
Expansion Bus
Byte Enables
Write Strobe
Read Strobe
Address Latch Enable
Expansion Bus
Interrupt
Hold Request
(Bus Request)
Hold Acknowledge
(Bus Grant)
Bus Grant Acknowledge
Signal Name
Mindspeed Technologies
t/s I/O
t/s O
t/s O
t/s O
t/s O
t/s O
t/s O
t/s O
I/O
I
I
ECLK is an inverted version of the PCI clock applied at the PCLK input.
EAD[31:0] is a multiplexed address/data bus. During the address phase,
pins EAD[17:0] contains meaningful address information. It is the same
address as PCI AD[19:2] for the corresponding cycle.
Pins EAD[31:18] are driven to 0 during the address phase. This is because
those upper bits are compared, during the PCI address phase, to the value
in the relocatable EBUS Base Address register to determine if the PCI cycle
is in fact addressing into MUSYCC EBUS space.
During data phase of an EBUS access cycle, the PCI signals AD[31:0] are
transferred to the EBUS signal lines EAD[31:0] unaltered.
EBE* contains the same information as the PCI byte enables but is driven
in chip select style protocol used as active-low chip selects when
MUSYCC is connected to more than one byte-wide device. All PCI
accesses with byte lane 0’s byte enable asserted would go to the byte-
wide device connected to EAD[7:0]. Likewise, for byte lanes 1, 2, and 3
and EAD[15:8], EAD[23:16], and EAD[31:24], respectively.
Only the CBE[3:0]* signals from the PCI data phase (byte-enable signals
and not the command signals from the PCI address phase) are transferred
to the EBE[3:0]* signal lines. EBE* is held high during all other phases of
PCI access cycles.
High-to-low transition enables write data from MUSYCC into peripheral
device. Rising edge defines write. (In Motorola mode, R/WR* is held high
throughout read operation and held low throughout write operation.
Determines meaning of DS* strobe.)
High-to-low transition enables read data from peripheral into MUSYCC.
Held high throughout write operation. (In Motorola mode, DS* transitions
low for both read and write operations and is held low throughout the
operation.
High-to-low transition indicates that EAD[31:0] bus contains valid
address. Remains asserted low through the data phase of the EBUS
access. (In Motorola mode, high-to-low transition indicates EBUS
contains valid address. Remains asserted for the entire access cycle.)
EINT* transfers interrupts from local devices to the PCI INTB* pin.
When asserted, MUSYCC requests control of the EBUS.
When asserted, MUSYCC has access to the EBUS. It is held asserted when
there are no other masters connected to the bus, or asserted as a
handshake mechanism to control EBUS arbitration.
When asserted, MUSYCC acknowledges to the bus arbiter that the bus
grant signal was detected and a bus cycle will be sustained by MUSYCC
until this signal is deasserted.
®
Definition
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