28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 120

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 5-31.
5.2.5.3
The Interrupt Status Descriptor is located in a fixed position within MUSYCC’s internal registers. MUSYCC updates
this descriptor after each transfer of interrupt descriptors from its internal queue to the Interrupt Queue in shared
memory. The host must read this descriptor from MUSYCC registers before it processes any interrupts. The
interrupt status descriptor’s contents are reset on hardware reset, soft chip reset, or when any field in the Interrupt
Queue Descriptor is modified.
Table 5-32
Table 5-32.
28478-DSH-002-E
FOOTNOTE:
(1)
(2)
(3)
Field
13:0
Field
30:16
Bit
14
Bit
31
Receive EOB and Receive EOM are concurrent events and are reported as a single interrupt; whereas Transmit EOB and EOM are separate
events and are reported as separate interrupts (two interrupt events).
Interrupt names are also reported in an error field within a receive Buffer Status Descriptor which indicates the transfer status of a
message currently being processed on a channel. The order of appearance in shared memory of a Buffer Status Descriptor and an
Interrupt Descriptor carrying the same error condition information is indeterminate. The host should confirm that both an Interrupt
Descriptor and a Buffer Status Descriptor reports the error condition.
Previously existed in bit 14 of 8474, 8472.
BLEN[13:0]
lists the details of the Interrupt Status Descriptor.
GRP[2]
NEXTINT[14:0]
Name
Field
Interrupt Descriptor (5 of 5)
Interrupt Status Descriptor
Name
RSVD
NOTE:
Interrupt Status Descriptor
Value
Preliminary Information / Mindspeed Proprietary and Confidential
If the Interrupt Queue is full, writing back the same index (NEXTINT) will not allow future
updates. Hence, the host cannot process any interrupts from MUSYCC including SACK.
To overcome this, if the interrupt Queue is full, the following is required:
Please refer to the CN847x driver software for the pseudocode.
Value
—
0
Interrupt
1. The 'next' (NEXTINT) value must first be writen to a different value (next-1) and
2. Then the correct value.
Name
Reserved.
Next Interrupt Index. 15-bit dword index, or offset, from start of Interrupt Queue up to where the host
has serviced Interrupt Descriptors. The NEXTINT is a read/write bit field. This is a 0-based number
and equals the dword offset from Interrupt Queue Pointer.
The host can read this value to get the location of the first unserviced descriptor in the queue. As
the queue is circular, care must be taken to ensure roll-over cases at beginning and end of
queue. The host must update this field with the value of the next available entry in the Interrupt
Queue after processing interrupts.
Mindspeed Technologies
—
—
MSB of Group number.
This field is relevant when EVENT field is EOB (Rx and Tx) or EOM (Rx
only). For Rx, it is equal to the number of octets received. For Tx, it is
the size of the buffer length targeted for transmission and not
necessarily the number of octets transmitted. This field is 0 all other
times.
®
Description
Description
Memory Organization
107