28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 57

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

The master’s latency timer specifies the maximum number of PCI clock cycles that the master can (and in the case
of MUSYCC, will) keep the bus after starting the access cycle by asserting its FRAME*. The latency timer also
ensures that the master has a minimum time slot for it to own the bus, but places an upper limit on how long it will
own the bus. In MUSYCC, the Latency Timer is reset to 0 on PRST* (PCI reset).
Once the bus is acquired and bursting begins, PCI throughput becomes the point of focus. MUSYCC is capable of
multi-dword bursts (read or write). As each FIFO buffer for a logical channel and direction is serviced on the PCI,
MUSYCC relinquishes and then reacquires the bus to service the FIFO buffer of the next logical channel. If more
logical channels are serviced, bus turnover is increased, which decreases throughput (but does not necessarily
affect service). If fewer logical channels are serviced, bus turnover decreases, and that increases throughput (but
not necessarily to the benefit of channel processing).
Refer to Chapter 3 of the PCI Local Bus Specification, Revision 2.1, for a description of bandwidth and latency
considerations.
2.2.6.1
The latency that a PCI master encounters as it tries to gain access to the PCI bus has three components:
1. Arbitration latency: usually 2 clock cycles for a high priority device, but is added into the total latency time only
2. Bus acquisition latency: length of time a device must wait for the bus to become free.
3. Target latency: length of time the selected target takes to assert TRDY* for the first data transfer.
The longest latency MUSYCC experiences in gaining access to the PCI bus is
or [k x (T + 8)] when all T
Once a master gets the bus, it starts a count-down timer loaded with the value T, from the latency timer register.
When the count reaches 0, the master relinquishes the bus when its GNT* is removed and it sees TRDY* on the
final data phase. As long as its GNT* is still asserted, the master is free to burst indefinitely.
example of PCI latency.
Table 2-17.
28478-DSH-002-E
0
+1
+1
T = the value of the latency timers in those masters
8 = the longest target latency allowed, in clock cycles (exception: the first data phase is allowed 16 clock
k = the number of PCI masters in the system
if the bus is idle when a device requests it, otherwise, it overlaps with the bus acquisition latency.
PCI Clock Increment
cycles)
PCI Latency Example (1 of 2)
PCI Bus Latency
i
s are equal, where:
Preliminary Information / Mindspeed Proprietary and Confidential
Bus is idle.
Host asserts REQ*.
MUSYCC asserts REQ*.
Host gets GNT*.
Host asserts FRAME* to start access cycle.
Mindspeed Technologies
Latency
Total
=
k 1
i
∑
=
–
0
(
Bus Activity
T
®
i
+
8
These 2 clock cycles are the arbitration latency that
becomes 0 if the bus was not idle.
)
Table 2-17
Host Interface
provides an
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