28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 129

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

6.2.6.2
There are only a few locations that are allowed to be slave-accessed after MUSYCC has an active channel:
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The host must not perform PCI slave accesses to any other register after MUSYCC has a channel activated on any
group. Any attempt to read or write to other MUSYCC registers as a PCI slave device while channels are activated
can result in DMAC lock-up and spontaneous (unreported) channel deactivation. This limitation is inclusive of all
groups; for example, it is not acceptable to perform a slave write to the group 2 time slot map while there is an
active channel on group 0.
All of the slave writes can be accomplished with initial service requests after setting the appropriate descriptor
value in shared memory. Also, any value that could be read directly from MUSYCC can more easily be read directly
from the descriptors in shared memory.
6.3
To start any channel processing, a series of shared memory segments must be obtained by the host and initialized
as specific descriptors which MUSYCC can use to control its channel processing operations.
To illustrate the required MUSYCC configuration, assume the following:
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28478-DSH-002-E
Group Base Pointer
Service Request Descriptor
Interrupt Status Descriptor
Any EBUS function 1 location
Port 0 is physically wired to a PCM carrying E1 signal (2.048 Mbps).
EBUS is not used.
PCI configuration is displayed in
Memory Protection is enabled for range 0x00100000 to 0x001FFFFF.
Application:
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C-Language support.
Each section below builds on the previous sections.
Port 0 is configured for 32 channel operation, E1 signal, 2.048 Mbps.
Transmit and Receive time slots are mapped identically.
Time slot 0 is mapped to logical channel 0 (64 kbps).
Time slot 1 bits 0–3 are mapped to logical channel 1 (32 kbps subchannel).
Time slot 2–3 are mapped to logical channel 2 (128 kbps hyperchannel).
16-bit FCS HDLC.
Maximum message length is 1024 octets for channel 0.
Maximum message length is 512 octets for channel 1.
Maximum message length check is disabled for channel 2.
No SS7 functions.
Idle Code = 7Eh.
Pad Fill Count = 0.
Memory Operations—Active Channels
Channel Operation
Preliminary Information / Mindspeed Proprietary and Confidential
Table 5-3, MUSYCC PCI Function Memory
Mindspeed Technologies
®
Allocation.
Basic Operation
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