28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 70

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

TDAT_EDGE bit fields (detailed in
Table 5-12, Port Configuration
The default, after device reset, is to sample in and latch out data, synchronization, and status on the falling edges
of the respective line clock.
4.2
The bit-level processors (Rx-BLP and Tx-BLP) service the bits in the receive and transmit path. As internal FIFO
buffers are filled and flushed, the BLP requests memory transfers from the DMAC. The BLP coordinates all bit-
level transactions between SERI and DMAC. The BLP also interacts with the INTC to notify the host of events and
errors during bit-level processing.
4.3
The DMA controllers (Rx-DMAC and Tx-DMAC) manage all memory operations between a corresponding BLP and
the host interface. DMAC takes requests from BLP to either fill or flush internal FIFO buffers, sets up an access to
data buffers in shared memory, and requests access to the PCI bus through the host interface.
4.4
The interrupt controller takes receive and transmit events from Rx-BLP and Tx-BLP, respectively. The INTC
coordinates the transfer of internally queued descriptors to an interrupt queue in shared memory and also
coordinates the notification to the host of pending interrupts.
4.5
Each SERI can be configured independently using the PORTMD bit field (see
Descriptor).
Channelized mode refers to a data bit stream segmented into frames. Each frame consists of a series of 8-bit time
slots. Typically, each frame recurs every 125 µs at an 8 kHz rate. MUSYCC maintains frame synchronization in
both the transmit and receive directions by using the TSYNC and RSYNC input signals. In addition, the ROOF
input signal can be used to notify MUSYCC of the loss of frame synchronization.
Table 4-1
Table 4-1.
28478-DSH-002-E
Mode
2 E1
T1
E1
describes the contents of a typical 8 kHz frame in each of the possible channelized port modes.
Channelized Serial Port Modes
Clock Frequency
Bit Level Processor
DMA Controller
Interrupt Controller
Channelized Port Mode
1.544 MHz
2.048 MHz
4.096 MHz
Preliminary Information / Mindspeed Proprietary and Confidential
Descriptor).
Mindspeed Technologies
Bits per Frame
193
256
512
Single frame bit, followed by 24 time slots, numbered TS0–TS23.
32 time slots, numbered TS0–TS31.
64 time slots, numbered TS0–TS63.
®
Table 5-12, Port Configuration
Description
Serial Interface
57