28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 33

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Figure 1-12. CN8478 Logic Diagram
28478-DSH-002-E
FOOTNOTE:
(1)
(2)
(3)
(4)
(5)
8478_004
EBE [3:0]* pin numbers are 199-200, 203-204.
EAD [31:0] pin numbers are 144-146, 149-152, 145-155, 158-163, 166-170, 173-174, 176-180, 183-184, 187-189.
AD [31:0] pin numbers are 48-51, 54, 56-58, 61-62, 65-66, 69-72, 88, 90-94, 97, 99, 101-103, 105-109.
CBS [3.0]* pin numbers are 59, 74, 87,100.
An active low signal is denoted by a trailing asterisk (*).
Initialization Device Select
Expansion Bus Interrupt
Bus Grant Acknowledge
Address and Data Bus I/O
Address Latch Enable
Hold Acknowledge
Write Strobe/Read
JTAG Mode Select
Synchronization
Synchronization
Synchronization
Synchronization
Synchronization
Synchronization
Synchronization
Synchronization
JTAG Data Out
Initiator Ready
Out-Of-Frame
Out-Of-Frame
Out-Of-Frame
Out-Of-Frame
Out-Of-Frame
Out-Of-Frame
Out-Of-Frame
Device Select
Hold Request
Out-Of-Frame
Target Ready
JTAG Data In
Read Strobe
JTAG Reset
JTAG Clock
Parity Error
M66EN
Frame
Reset
Parity
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Grant
Data
Data
Data
Data
Data
Data
Data
Data
Stop
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O 192
O
Preliminary Information / Mindspeed Proprietary and Confidential
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198
197
196
195
194
193
207
208
10
17
18
19
20
25
26
29
30
11
12
15
16
22
23
24
31
32
33
34
36
37
38
39
43
45
46
60
75
76
79
80
83
84
86
(3)
98
21
35
7
8
3
4
5
6
1
2
9
WR* (R/WR*)
BGACK*
HLDA (BG*)
HOLD (BR*)
EINT*
ALE* (AS*)
RD* (DS*)
ROOF[7]
RCLK[7]
RSYNC[7]
RDAT[7]
ROOF[6]
RCLK[6]
RSYNC[6]
RDAT[6]
ROOF[5]
RCLK[5]
RSYNC[5]
RDAT5]
ROOF[4]
RCLK[4]
RSYNC[4]
RDAT[4]
ROOF[3]
RCLK[3]
RSYNC[3]
RDAT[3]
ROOF[2]
RCLK[2]
RSYNC[2]
RDAT[2]
ROOF[1]
RCLK[1]
RSYNC[1]
RDAT[1]
ROOF[0]
RCLK[0]
RSYNC[0]
RDAT[0]
TCK
TRST*
TMS
TDO
TDI
PCLK
PRST*
GNT*
IDSEL
FRAME*
IRDY*
TRDY*
DEVSEL*
STOP*
PERR*
PAR
AD[31:0]
M66EN
Mindspeed Technologies
Boundary Scan
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Receive Serial
Receive Serial
Receive Serial
Receive Serial
Receive Serial
Receive Serial
Receive Serial
Receive Serial
Test Signal
7
6
5
4
3
2
1
0
Expansion Bus
Serial Interface
Host (PCI)
Interface
Interface
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Channel Group
Transmit Serial
Transmit Serial
Transmit Serial
Transmit Serial
Transmit Serial
Transmit Serial
Transmit Serial
Transmit Serial
Test Access
Scan Chain
7
6
5
4
3
2
1
0
®
EAD[31:0]
TSYNC[7]
TSYNC[6]
TSYNC[5]
TSYNC[4]
TSYNC[3]
TSYNC[2]
TSYNC[1]
TSYNC[0]
CBE[3:0]*
EBE[3:0]*
TCLK[7]
TCLK[6]
TCLK[5]
TCLK[4]
TCLK[3]
TCLK[2]
TCLK[1]
TCLK[0]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
SERR*
ECLK
INTB*
TM[0]
TM[1]
TM[2]
INTA*
REQ*
190
140
149
138
131
130
129
125
124
123
117
116
115
143
142
141
136
135
134
128
127
126
122
121
120
114
113
112
(4)
(1)
(2)
40
41
47
85
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
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O
Clock
Expansion Bus Byte Enable
Expansion Bus Address/Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Clock
Synchronization
Data
Scan Enable
Scan Mode Bit 1
Scan Mode Bit 2
PCI Interrupt B
PCI Interrupt A
Command and Byte Enables
Request
System Error
20