28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 157

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

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Channel Level Recovery Actions:
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6.4.8.4.3
In the case of a Change of Frame Alignment while receiving an HDLC message (T1/E1 modes
signal transitions from low to high unexpectedly by the “frame synchronization flywheel mechanism.” This error
applies only to ports configured for T1, E1, 2xE1, or 4xE1 signals. Frame synchronization indicates the location of
time slot 0 in the serial data stream. Lacking frame synchronization, the received channelized data becomes
unaligned and unmappable. This error affects all active channels in the channel group.
Reason:
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Effects:
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Channel Level Recovery Actions:
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28478-DSH-002-E
The received data in the internal FIFO buffer is discarded and lost to the host.
The remainder of HDLC message currently being received is discarded.
Access the Next Message Pointer from the Current Message Descriptor.
Return ownership of current Message Descriptor by writing the Receive Buffer Status Descriptor with
ONR = HOST, ERROR = BUFF (if INHRBSD = 0 in Receive Channel Configuration Descriptor).
BLP scans for the opening flag of the next HDLC message.
Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared
memory.
If possible, increase internal FIFO buffer space for this channel. For this action, the channel must be
deactivated first.
If required, alleviate congestion of the PCI bus.
T1/E1 signal failure is detected by the physical interface providing the serial data, clock frequency, and
synchronization to the serial interface on MUSYCC.
Causes the serial interface to enter the COFA mode for one T1/E1 frame period (125 µs).
For each activated channel receiving an HDLC message, the remainder of the HDLC message currently being
received is discarded, and the receiver scans for the opening flag of the next HDLC message before attempting
to fill the channel’s FIFO buffer again.
For each activated channel receiving an HDLC message, the ownership of the current Message Descriptor is
granted back to the host by writing the Receive Buffer Status Descriptor with ONR = HOST and
ERROR = COFA (if INHRBSD = 0 in Receive Channel Configuration Descriptor).
After all activated channels are serviced, MUSYCC writes the Interrupt Descriptor in Interrupt Queue with
ERROR = COFA. DIR = 0 (if MSKCOFA = 0 in Group Configuration Descriptor).
After the COFA condition clears, normal bit-level operations continue.
The BLP scans for the opening flag of the next HDLC message.
Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared
memory.
None required.
Change of Frame Alignment (COFA) while Receiving HDLC Message
(T1/E1 modes)
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
)
Basic Operation
, the RSYNC input
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