28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 71

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 4-1.
Port mode only defines the number of bits per TDM frame. It does not restrict the clock frequency to the
corresponding mode frequencies. Independent of the mode, each port is capable of operating up to a clock
frequency of 8.192 MHz. For example, a port can be configured to an E1 mode, or 256 bits per frame, and has a
clock frequency of 8.192 MHz. This means that each frame recurs every 31.25
10
how often the sync pulses must be generated toward TSYNC and RSYNC in order for MUSYCC to maintain frame
synchronization when in external frame alignment (SFALIGN = 1, see Group Configuration Descriptor.
4.5.1
A hyperchannel is a logical channel consisting of multiple time slots concatenated. That is, bits from one or more 8-
bit time slots within a frame are assigned to one logical channel. A hyperchannel can be set up in any port mode,
provided that there are sufficient number of time slots in the frame, which is configured by port mode, to achieve
the desired data rate. A hyperchannel can comprise from 1–128 time slots. This results in one logical channel
supporting an Nx64 kbps bit rate where the actual data rate can range between 64 kbps and 8.192 Mbps. The
concatenated time slots need not be contiguous.
Hyperchanneled time slots assigned to the same logical channel number within a channel group (0–31) are
required for proper support.
The Time Slot Descriptor enables and assigns a time slot to a logical channel (see
Descriptor). The configurations for receive and transmit hyperchannels are independent.
4.5.2
A subchannel results from treating each bit in an 8-bit time slot independently and assigning a logical channel
number to each active bit. Not all 8 bits need to be active, and any combination of bits within the 8 in a time slot can
be assigned to the same logical channel number. Similarly, multiple time slots can supply one or more bits to
comprise one subchannel. This results in one logical channel supporting an Nx8 bit rate between 8 kbps to 64 kbps
in multiples of 8 kbps. The following configurations are required to support subchannels:
•
•
•
The Time Slot Descriptor
and each individual bit within the time slot to a logical channel. The configurations for receive and transmit
subchannels are independent.
The Time Slot Descriptor assigns bit 0 of a time slot to a logical channel. The Subchannel Descriptor assigns bits 1
through 7 of a time slot to a logical channel.
28478-DSH-002-E
GENERAL NOTE:
6
Mode
bits) = 31.25 KHz) at a 32 KHz (8.192 MHz / 256 = 32 KHz) sampling rate. The 31.25
Each active bit is assigned a logical channel number within a channel group (0–31).
Each time slot with active bits must be enabled in the Time Slot Map.
Each active bit (after the first bit, bit 0) must be enabled in the Subchannel Map.
Nx64
4 E1
Nx64 mode allows MUSYCC to accommodate frame sizes that are not pre-defined (T1, E1, 2E1, 4E1).
Channelized Serial Port Modes
Clock Frequency
Hyperchannels (Nx64)
Subchannels (Nx8)
(1 ≤ N ≤ 128)
8.192 MHz
Nx64 kHz
(Table
Preliminary Information / Mindspeed Proprietary and Confidential
5-15), and the Subchannel Descriptor
Mindspeed Technologies
Bits per Frame
(1 ≤ N ≤ 128)
1024
Nx8
128 time slots, numbered TS0–TS127.
N time slots, numbered TS0–TSN-1.
®
(Table
5-17), enable and assign a time slot
µ
s (256 bits x (1 second / 8.192 x
Description
Table 5-15, Time Slot
µ
s frame recurrence is
Serial Interface
58