28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 155

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

•
•
Channel Level Recovery Actions:
•
6.4.8.3.2
In the case of underflow due to internal FIFO buffer under-run, the internal FIFO buffer becomes empty when
MUSYCC transmits data bits (at the serial interface clock rate), and MUSYCC has ownership of a message buffer
in shared memory.
Reasons:
•
•
Effects:
•
•
•
•
Channel Level Recovery Actions:
•
6.4.8.3.3
In the case of change of frame alignment while transmitting an HDLC message (T1/E1 modes), the TSYNC input
signal transitions from low to high when not expected to do so by the frame synchronization flywheel mechanism.
This error only applies to ports configured for T1, E1, 2xE1 or 4xE1 signals. Frame synchronization indicates the
location of time slot 0 in the serial data stream. Lacking frame synchronization, the transmitter cannot map and
align time slots. This error affects all active channels in the channel group.
Reason:
•
Effects:
•
•
•
•
•
28478-DSH-002-E
Message polling is automatically disabled.
Transmit channel enters abort state.
Transmit channel reactivation is required.
Degradation of the host subsystem or application software performance.
Congestion of the PCI bus.
Interrupt Descriptor in Interrupt Queue with ERROR = BUFF, DIR = 1
(if MSKBUFF = 0 in Transmit Channel Configuration Descriptor).
Transmit channel enters abort state where the BLP transmits a repetitive abort sequence of 16 consecutive 1s.
Message polling is automatically disabled.
Transmit Buffer Status Descriptor is not written.
Transmit channel reactivation is required.
T1/E1 signal failure is detected by the physical interface providing the serial data, clock frequency, and
synchronization to the serial interface on MUSYCC.
Causes serial interface to enter COFA mode for one T1/E1 frame period (125 µs)—not necessarily on a frame
boundary.
For every activated channel transmitting an HDLC message, the Transmit channel enters an abort state where
the BLP transmits a repetitive abort sequence of 16 consecutive 1s.
MUSYCC does not update the transmit Message Descriptor and does not generate an EOB/EOM unless the
message is already sent or the buffer is already processed.
MUSYCC stops polling any active transmit channels descriptor.
After the COFA condition subsides, the channel is deactivated.
Underflow Due to Internal FIFO Buffer Under-Run (BUFF)
(T1/E1 modes)
Change of Frame Alignment (COFA) while Transmitting HDLC Message
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Basic Operation
142